KL26Z 5V Tolerant Inputs

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

KL26Z 5V Tolerant Inputs

1,286 Views
tarikaweimrin
Contributor III

“The Kinetis Port pins are only 5V tolerant as inputs. The outputs are not 5V tolerant, and that includes pins configured as open-drain outputs. In output mode, if the pin is pulled above VDD, it will cause the output buffer to drive the output at VDD, which will pull-down the pin voltage to near VDD.”

I ran across this comment in a previous thread.

I want to configure a GPIO on the KL26Z we are using as a Hi-Z input (no internal pull up or down) that is externally pulled up to 5V through >20Kohm resistors and then to simulate button presses by turning that GPIO to a low output then back to a Hi-Z input. From the previous comment it seems that this is reasonable if the pins are 5V tolerant as inputs. I wanted to confirm this, or find where I am mistaken.

Also, I have scoured KL26 datasheets for the technical data that would support this if confirmed and can’t find any references. Is this documented somewhere?

Labels (1)
0 Kudos
Reply
5 Replies

1,121 Views
jingpan
NXP TechSupport
NXP TechSupport

Hi Tarik,

But there is no words say KL26 is 5v tolerant. The max input voltage is 3.6V. Please don't connect 5v signal. 

Regards,

Jing

0 Kudos
Reply

1,121 Views
tarikaweimrin
Contributor III

Kinetis 5V I2C interface 

In the thread posted above it mentions if the GPIO is configured as an input for Kinetis series it would be 5V tolerant.  I have this working with no damage on the freedom board for the KL26Z.  I see that for the K64 and other in the kinetis series denotes 5V tolerant inputs in datasheets, is the KL26Z different?

0 Kudos
Reply

1,121 Views
jingpan
NXP TechSupport
NXP TechSupport

Hi,

No, not all kinetis have 5v tolerant pin.

pastedImage_1.png

This is table 5 in KL26 datasheet.

Yes, I agree pullup through a 20k resistor to 5V can protect the pin. The current is very small. Since there isn't ESD to VDD, there isn't current to VDD also.

Regards,

Jing

0 Kudos
Reply

1,121 Views
tarikaweimrin
Contributor III

I understand it is not recommended.  I just want to know if it will cause damage.  In the "Off State" as an input with the external resistor there should be little current to damage the chip.  In the "On State" the GPIO is configured as a low output.  I don't think either state would damage the chip.  I just want to see if I am overlooking something.

pastedImage_1.png

0 Kudos
Reply

1,121 Views
jingpan
NXP TechSupport
NXP TechSupport

Hi,

I think it's fine.

Regards,

Jing

0 Kudos
Reply