Hello Kris,
[A1]
The user margin is a small delta to the normal read reference level and, in effect, is a minimum safety margin. If the reads pass at the tighter tolerances of the user margins, then the normal reads have at least some safety margin before users experience data loss. There are two user margin levels: user margin-1 level and user margin-0 level. User margin-1 level is the read margin to the erased state, while user margin-0 level is the read margin to the programmed state.
The following is a summary for understanding margin operation.
a) Erase Verify level is used by MCU. After erase operation MCU checks the contents using this level.
Program Verify level is same.
b) NR(Normal level) is a threshold level which decides whether flash data is "0" or "1".
If voltage value of flash cell is higher than NR, this bit is "1".
If voltage value of flash cell is lower than NR, this bit is "0".
c) Margin 0 level is for checking programming operation. (for flash data = 1).
Confirming a depth of programmed flash bit cell.
If it passed Factory Margin read 0, this means the programmed flash bit cell has
Higher voltage (more deep).
Margin 0 is same but it relates for Erase operation.
Attached to this mail, you can find a picture which indicate the level of margin.
The margin selection depends on customer requirement.
[A2]
Yes, when execute the erase flash sector finished, it will automatically execute erase_verify and if erase failed, FSTAT_MGSTAT0 bit will be automatically set.
[A3]
The Read 1s Section Command will check a section of program flash or data flash memory is erased to the specified read margin level.
The phrase size is 8 bytes, this command can check customer required numbers of phrase Flash memory size.
Such as, customer can verify 1 sector Flash size.
number = FTFx_PSECTOR_SIZE/DRD1SEC_ALIGN_SIZE;
/*! @brief P-Flash sector size */
#define FTFx_PSECTOR_SIZE 0x00000800U /* 2 KB size */
/*! @brief FlexNVM read 1s section command address alignment */
#define DRD1SEC_ALIGN_SIZE FTFx_LONGWORD_SIZE
/*! @brief Phrase size */
#define FTFx_PHRASE_SIZE 0x0008U /* 8 bytes */
[A4]
After you launch the flash operation command by writing 1 to CCIF, then you can use this code to wait the flash operation is completed:
FTFA_FSTAT = FTFA_FSTAT_CCIF_MASK;
while(!(FTFA_FSTAT & FTFA_FSTAT_CCIF_MASK));
Actually it is the same as your while(read_CCIF == 0)().
If your code is correct, the CCIF can be set after the flash command has completed.
About the flash execute fails, yes, if you enable the cpu interrupt or don't put the launch command operation in the RAM, the flash operation may be fail, can then the cpu will work unnormal, may be enter hardfault interrupt.
So, please put the flash commander launch operation function in the RAM, and disable the interrupt when you do flash operation.
[A5]
Of course the FCMD support erase block, read 1s block, it also support erase flash sector command, program longword command etc.
For details, please refer to the according reference manual, chapter FTFA, Flash command description, you will get the detail command and write sequence.
Take KL25 as an example(I don't know which kinetis chip you are using):
FCMD =0X01: Read 1s Section
FCMD =0X02:Program Check
FCMD =0X03:Read Resource
FCMD =0X06:Program Longword
FCMD =0X09:Erase Flash Sector
FCMD =0X40:Read 1s All Blocks
FCMD =0X41:Read Once
FCMD =0X43:Program Once
FCMD =0X44:Erase All Blocks
FCMD =0X45:Verify Backdoor Access Key
[A6]
Please check the below application note, this may helps
http://cache.freescale.com/files/microcontrollers/doc/user_guide/KBTLDRUG.pdf
Please let me know if this helps!
Have a great day,
Sol
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
