How to set clock to 48Mhz (KL25Z4)

[frederik_sebast]

Board: KL25Z4

Hey, 

me and my team are having problems setting the clock from the default mode to 48 Mhz using the external crystal that the the board comes with.

I saw that there is a clock set up routine in the start up code (system_MKL25Z4.c and system_MKL25Z4.h) already given and that a routine will be executed based on the definition of CLOCK_SETUP which is not defined by default. So I just defined CLOCK_SETUP as 2 in order to go into PEE mode and have a clock frequency of 48 Mhz. However, when I run the code, reset mode is entered. 

So how can I make the system set up to run with 48 Mhz clock frequency?

Any help here is appreciated! Thank you very much.

Best regards,

Frederik

[Robin_Shen]

Hi Frederik,

MCUXpresso Software and Tools are recommended for customers.
The Clocks tool of MCUXpresso IDE is able to generated the these codes.

You need to download the MCUXpresso SDK for KL25 and the latest MCUXpresso IDE.

You can refer the: Quick Start Guide – Using MCUXpresso SDK with PINs&CLOCKs Config Tools

Best Regards,

Robin

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[frederik_sebast]

Hey Robin,

thanks again. We now switched to MCUXpresso and it works perfectly fine!

It also works on MacOs which is even better.

Best regards,

Frederik

[frederik_sebast]

Thank you very much.

I am using Kinetis Design Studio as IDE. Is there an easy way to use the existing resources there in order to change the clock frequency? 

Best regards,

Frederik

[mjbcswitzerland]

Hi

uTasker works with KDS.

User configuration for KL25:
#define OSC_LOW_GAIN_MODE   // oscillator without feedback resistor or load capacitors so use low gain mode
//#define RUN_FROM_LIRC     // clock from internal 4MHz RC clock
//#define RUN_FROM_DEFAULT_CLOCK  // run from FLL default setting
//#define RUN_FROM_EXTERNAL_CLOCK // run directly from external 8MHz clock (without PLL)
#define CRYSTAL_FREQUENCY    8000000  // 8 MHz crystal
#define CLOCK_DIV       4   // input must be divided to 2MHz..4MHz range (/1 to /25 possible)
#define CLOCK_MUL        48   // the PLL multiplication factor to achieve MCGPLLCLK operating frequency of 98MHz (x24 to x55 possible) (MCGPLLCLK/2 is 48MHz - required by USB)
#define SYSTEM_CLOCK_DIVIDE 2 // divide (1,2,3..16 possible) to get core clock of 48MHz
#define BUS_CLOCK_DIVIDE    2 // divide from core clock for bus and flash clock (1,2,3..8 possible) 24MHz
#define FLASH_CLOCK_DIVIDE  2

#define USB_CLOCK_GENERATED_INTERNALLY  // use USB clock from internal source rather than external pin

Values can be changes to suit any configuration and speed and it will tell you if anything is not legally set and generate the approx. 10 lines of code needed.

If you need a graphical tool to generate the approx. 10 lines of code you will need to use PE or MCUXpresso and copy the code into your environment.

Alternatively read the MCG chapter in the user's manual and set the registers as explained there.

Regards

Mark

[mjbcswitzerland]

Hi Frederik

For KL25 on FRDM-KL25Z with 8MHz crystal

MCG_C2 = (MCG_C2_FREQ_RANGE | MCG_C2_GAIN_MODE | MCG_C2_EREFS | MCG_C2_LOCRE0); // select crystal oscillator and select a suitable range
MCG_C1 = (MCG_C1_CLKS_EXTERN_CLK | MCG_C1_FRDIV_VALUE);              // switch to external source (the FLL input clock is set to as close to its input range as possible, although this is not absolutely necessary if the FLL will not be used)
while ((MCG_S & MCG_S_OSCINIT) == 0) {}                              // loop until the crystal source has been selected
while ((MCG_S & MCG_S_IREFST) != 0) {}                               // loop until the FLL source is no longer the internal reference clock
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXTERN_CLK) {}      // loop until the external reference clock source is valid
MCG_C5 = ((CLOCK_DIV - 1) | MCG_C5_PLLSTEN0);                        // now move from state FEE to state PBE (or FBE) PLL remains enabled in normal stop modes
MCG_C6 = ((CLOCK_MUL - MCG_C6_VDIV0_LOWEST) | MCG_C6_PLLS);          // set the PLL multiplication factor
while ((MCG_S & MCG_S_PLLST) == 0) {}                                // loop until the PLLS clock source becomes valid
while ((MCG_S & MCG_S_LOCK) == 0) {}                                 // loop until PLL locks
SIM_CLKDIV1 = (((SYSTEM_CLOCK_DIVIDE - 1) << 28) | ((BUS_CLOCK_DIVIDE - 1) << 16)); // prepare bus clock divides (flash and bus clocks are the same)
MCG_C1 = (MCG_C1_CLKS_PLL_FLL | MCG_C1_FRDIV_1024);                  // finally move from PBE to PEE mode - switch to PLL clock
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL) {}             // loop until the PLL clock is selected
‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍‍

Note that for the HW on the FRDM-KL25Z
#define MCG_C2_GAIN_MODE    0                                        // don't select high gain mode since the oscillator will not start
and not
#define MCG_C2_GAIN_MODE    MCG_C2_HGO                               // select high gain mode
and
#define MCG_C2_FREQ_RANGE   MCG_C2_RANGE_1M_8M
for 8MHz crystal

#define CLOCK_DIV            4                                       // input must be divided to 2MHz..4MHz range (/1 to /25 possible)
#define CLOCK_MUL           48                                      // the PLL multiplication factor to achieve MCGPLLCLK operating frequency of 98MHz (x24 to x55 possible) (MCGPLLCLK/2 is 48MHz - required by USB)
For the KL25
#define MCG_C6_VDIV0_LOWEST  24

All other defines should be clear from their name and reference in the user's manual.

Get the complete code from the uTasker open source project on GitHub (with KL25 simulation - see below) in case of difficulties (or to simply accelerate your complete project work).

Regards

Mark

Complete Kinetis KL25 solutions, training and support: http://www.utasker.com/kinetis.html
Kinetis KL25:
- http://www.utasker.com/kinetis/FRDM-KL25Z.html
- http://www.utasker.com/kinetis/TWR-KL25Z48M.html