General switching specifications comprehension

[christophevigny]

I've got trouble understanding the General switching specification of the Kinetis devices.

For example the K20P144M120SF3, chap 5.3.2, Table 10 tells that "GPIO pin interrupt pulse width  Asynchrone (digital glitch and analog filter disabled) takes >16ns". I understand it's the minimum uptime of the PWM before the interrupt is raised.

But what I don't understand is the 8ns values for port rise and fall time. What do they represent?

What is tio50 and tio60 in that same table?

[christophevigny · Accepted solution]

I had some trouble understanding that table.

Some lines defined the interrupt trigger speed needed from an input.

Other lines defined the time needed to control a pin state as an output.

This was a bit confusing since not clearly stated.

[apanecatl]

Tio describes the time the port  ramp up / ramp down takes to go from VSS or VDD to its valid assertion level depending on the desired logical value [0 or1], this is defined by the inter GPIO circuitry and is categorized in two different power supply ranges:

• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V

For general I/O purposes you only need to take into consideration the first set of values in low and high strength, disregard Tio50 and Tio60. Tio60 describes the port rise/fall characteristics for the 60MHz ULPI interface assigned to pins PTA6-11 and PTA24-29.