FTM Capture not working as expected

DaveTonyCook

Hi,

I don't understand why using the system clock in my calculation of CHnFVAL[3:0] doesn't work but using System Clock /2 does. Implemented code provided.

SystemClk = 120MHz; Pre-scaler = divide by 1

Filter:

The signal to be captured by FTM1 Ch0 is Freq_Mon = 1MHz.
The signal when present has been verified by oscilloscope.

The minimum pulse width to be passed by the filter is:

1/2 Freq_Mon = 500ns.

From the manual [Ref: P972 K24 Sub-Family Reference Manual, Rev. 2, January 2014]
it states that:

minimum pulse width = CHnFVAL[3:0] x 4 system clocks

4 system clocks = 1/120MHz x 4
= 8.3ns x 4
= 33.33ns

so

CHnFVAL[3:0] = 500ns / 33.33ns
= 15 // Stops capturing. Tried 14 and get same result

However:

Setting CHnFVAL[3:0] = 7 passes a pulse of 500ns
Setting CHnFVAL[3:0] = 8 stops a pulse of 500ns

This infers the system clock is divided by 2. i.e. 60MHz

e.g.

4 system clocks = 1/60MHz x 4
= 16.67ns x 4
= 66.67ns

so

CHnFVAL[3:0] = 500ns / 66.67ns
= 7.5 (7) works fine, but I don't understand why?

Implementation: NB: the ISR is started every 500ms by the application code. The ISR disables itself every 2nd rising edge.

void FTM1_DRV_InputCaptureInit(void)
{
    // Enable clock to the FTM1 module
    SIM_SCGC6 |= SIM_SCGC6_FTM1_MASK;
    
    // Configure pin 64 and its alternate function for FTM1 Ch 0. pin PTA12 (64)    
    PORTA_PCR12 = PORT_PCR_MUX(3);
    
    // Disable write protection for FTM1 registers
    FTM1_MODE |= FTM_MODE_WPDIS_MASK;
    
    // Configure FTM1 as input capture
    FTM1_SC = 0;                        // Ensure FTM1 is disabled for setup
    FTM1_SC &= ~FTM_SC_TOIE_MASK;       // Disable Timer Overflow Interrupt
    FTM1_SC &= ~FTM_SC_TOF_MASK;        // Clear Timer Overflow Event flag
    FTM1_CNTIN = 0;                     // Count reset to 0
    FTM1_MOD = 0xFFFF;                  // Set the modulo register for maximum count

    // The clk source is set to 120MHz by FTM1_DRV_CaptureStart() every 500ms.    
    FTM1_SC &= ~FTM_SC_CLKS(7);         // Select NO clock.
    FTM1_SC |= FTM_SC_PS(0);            // Select prescaler divide by 1.
    
    // Configure FTM1 Channel 0 for input capture on rising edge only
    FTM1_C0SC = FTM_CnSC_ELSA_MASK;     // Capture on rising edge
       
    FTM1_FILTER |= FTM_FILTER_CH0FVAL(7);  // Half the input period
                                           // (120MHz / 4) x FVAL = 500ns 
                                           // FVAL = 500 / 33.33 = 15.
                                           // This value stops the ISR
                                           // (Using 60MHz / 4) x FVAL = 500ns
                                           // FVAL = 500 / 66.67 = 7.5
                                           // Use 7 and runs ok
                                           // Dont know why using the value of
                                           // SYS_CLK doesnt work.
                                           // The frequency set in SC reg is SYS_CLK
                                            
#ifdef DEBUG_CPT
    // Enable CAPTEST mode for FTM1 (simulate input capture events internally)
    FTM1_CONF |= FTM_CONF_CAPTEST_MASK;
#endif

    /* Configure NVIC. Register interrupt into Ram Vector table */
    os_install_int_handler (g_ftmIrqId[HW_FTM1], FTM1_ISR);
    
    NVIC_SetPriority(FTM1_IRQn, 1); // ISR runs every 500ms for ?ns
    
    NVIC_ClearPendingIRQ(g_ftmIrqId[HW_FTM1]);
    
    /* Enable FTM interrupt in NVIC level.*/
    INT_SYS_EnableIRQ(g_ftmIrqId[HW_FTM1]);
    
    // Make sure these are reset at initailization.
    count = 0;
    freq_mon_fault = false;
}

oid FTM1_DRV_CaptureStart(void)
{
    //__ITM_EVENT8(1,1);   

    captureStarted = true;              // Used by PIT3 isr handler
    
    // Reset the counter
    FTM1_CNT = 0;
    
    // Start counter
    FTM1_SC   |= FTM_SC_CLKS(1);          // Select Sys clock. 120MHz
    FTM1_SC   |= FTM_SC_PS(0);            // Select prescaler divide by 1
    FTM1_C0SC |= FTM_CnSC_CHIE_MASK;     // Enable channel interrupts
}

xiangjun_rong

Hi,

First of all, I suppose that capture signal digital filtering uses the system clock, it is not related to the CLKS bits/PS bits in FTMx_SC.

Regarding the calculation of the digital filtering minimum pulse width = CHnFVAL[3:0] x 4 system clocks, assume the system clock frequency is 120mhz, the capture signal is 1MHz,

the formula is correct.

CHnFVAL[3:0] = 500ns / 33.33ns
= 15 // Stops capturing. Tried 14 and get same result

Pls check the actual system clock frequency,you can output the flash clock to the CLKOUT pin, then calculate the system clock by checking the SIM_CLKDIV1 reg.

Hope it can help you

BR

XiangJun Rong

DaveTonyCook

Hi,

All CLKOUT pin possibilities are used for other system functions and have already been routed on the PCB making it difficult to isolate a likely candidate. I chose to reassign pin 58 on the 144pin LQFP K24 device from TRACE_CLKOUT to CLKOUT.

Using this pin allows connection of scope to the debug header which is easily accessible on our board. It does however disable the debugger so the status of the SIM_CLKDIV1 reg. must be determined before the pin reassignment.

From debugger register view I get:

SIM_CLKDIV1 reg. value = 0x104 i.e. OUTDIV2 = 0x1; OUTDIV4 = 0x4:

OUTDIV4 = 0x4 sets Flash CLK = SysCoreClk / 5

Routing the flash clock to pin 58 as follows:

// Configure pin 58 as CLKOUT
PORTA_PCR6 = PORT_PCR_MUX(5)

// Output flash clock to CLKOUT pin 58
SIM->SOPT2 |= SIM_SOPT2_CLKOUTSEL(2);

Measure Flash CLK on CLKOUT at pin 58 gives 25MHz as expected

OUTDIV4 = 0x4 sets Flash CLK = SysCoreClk / 5

= 120MHz / 5

= 25MHz by calculation

This verifies that the System Core Clock is in fact 120MHz so what is causing the problem. Why does setting CHnFVAL[3:0] = 15 Stop capturing?