Estimating DMA controller load

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Estimating DMA controller load

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Senior Contributor II

I'm making fairly heavy use of DMA in a project, considerably more than I've used in any previous project.  I have high speed (>= 1 mbps) UART traffic, I2S, DAC and ADC samples, and probably SPI a little later.

I'm curious if there are any good tools or techniques for keeping an eye on how busy the DMA controller is, and ideally also how much load is hitting the bus.

The only idea I've come up with so far would be to set up a channel with the lowest possible priority to send alternating 1s and 0s to a GPIO, where it could be monitored with a logic analyzer, the idea being that any gaps in the pattern would represent times the DMA controller was busy with higher-priority requests.

Is that reasonable?  Are there other ways to approach it?  I've done a little searching and haven't come up with anything, but I may not be using the right search terms.



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NXP TechSupport
NXP TechSupport

Hi Scott,

I think your way sounds reasonable.

It also could using a PIT to periodic trigger the DMA as eDMA working pulse shows:


The DMA transfer could toggle a GPIO pin.

Customer could short the PIT period interval to check if the eDMA engineer could response the trigger.

If the eDMA with heavy load, the periodic trigger will be ignored.

More detailed info, please check below picture:


I attached a PIT periodic trigger DMA example for your reference.

Thank you for the attention.

Have a great day,
Ma Hui

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