Are Kinetis MCU's clocks gated

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Are Kinetis MCU's clocks gated

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342 次查看
markbrinkman
Contributor II

K26FN2M0VMD reference manual 'clocking diagram' shows clock gates on outputs of core, bus, flexbus/SDRAMC and flash clocks. Where are they in the memory map? SIM_SCGC6[0] is the flash clock gate enable bit. What about SIM_SCGC7 bits [3] and [0]? Per the diagram FlexBus and SDRAMC share the same clock gate. What about core and bus clock gates? Reference manual section 7.3.4 item 2 adds to the confusion by stating core, system and flash do not have clock gate controls. Please clarify.

thanks

Dino

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216 次查看
kerryzhou
NXP TechSupport
NXP TechSupport

Hello MARK,

    About the clock, yes, you can see the clock diagram:

pastedImage_1.png

About the core clock, flash clock, flexbus clock ext. The gate is in the SIM module, you can use the SIM register to control the OUTDIV and gate.

Yes, SIM_SCGC6[0] is the flash clock gate enable bit.

SIM_SCGC7 bits [3] is the SDRAMC clock gate control,  and bit [0] is the flexbus clock gate control.

Diagram is the sketch map, the details register, you still need to check SIM chapter, normally, different module have different clock gate.

Core and bus is the chip main clock, so it doesn't have the SIM gate, you just need to control the OUTDIV, this is the divider.

chapter 7.3.4 item 2 is not very correct for MK26, this description is just copied from for other normal kinetis which don't have the gate, you can ignore it, but must make sure the according clock gate is enabled, actually, after reset, the flash clock is enabled in default, even you don't configure it, it still can be used, but when you use the sdram and the flexbus, you must enable it by yourself in the SIM registser.

When you do the code configuration, you totally can refer to our SDK sample code, that code has been tested.

Wish it helps you!


Have a great day,
Kerry

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216 次查看
markbrinkman
Contributor II

Thanks Kerry.

On a side note:

I've been working with various Kinetis MCU's over the years and questions are constantly arising because of 'cut' and 'paste' errors. I think your documentation error checking group needs to do a better job.

217 次查看
kerryzhou
NXP TechSupport
NXP TechSupport

Hello MARK,

    About the clock, yes, you can see the clock diagram:

pastedImage_1.png

About the core clock, flash clock, flexbus clock ext. The gate is in the SIM module, you can use the SIM register to control the OUTDIV and gate.

Yes, SIM_SCGC6[0] is the flash clock gate enable bit.

SIM_SCGC7 bits [3] is the SDRAMC clock gate control,  and bit [0] is the flexbus clock gate control.

Diagram is the sketch map, the details register, you still need to check SIM chapter, normally, different module have different clock gate.

Core and bus is the chip main clock, so it doesn't have the SIM gate, you just need to control the OUTDIV, this is the divider.

chapter 7.3.4 item 2 is not very correct for MK26, this description is just copied from for other normal kinetis which don't have the gate, you can ignore it, but must make sure the according clock gate is enabled, actually, after reset, the flash clock is enabled in default, even you don't configure it, it still can be used, but when you use the sdram and the flexbus, you must enable it by yourself in the SIM registser.

When you do the code configuration, you totally can refer to our SDK sample code, that code has been tested.

Wish it helps you!


Have a great day,
Kerry

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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