K32L3A60 Multicore Watchdog and debugging question

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

K32L3A60 Multicore Watchdog and debugging question

457 次查看
Dddd1
Contributor I

Hi All,

I am using K32L3A60 MCU on a custom board. Following, AN12673 Dual-Core Projects Application Note, we were able to create a multicore project and can debug both cores using MCUXpresso.

As an incremental step, I have now initialized WDOG0 and enabled it (not in windowed mode). Furthermore, I have set the config struct to config.workMode.enableDebug = false so that watchdog is disabled in chip debug mode (according to ref. manual regarding WDOG0 control and status register).

When I set a breakpoint in M4 core I and break and step thru the code as normal; however, if I set a breakpoint in M0+ core, and step thru the M0+ code, the M4 gets watchdog reset (I check the System Reset Status (SRS) register and indeed the register's 13th bit is set, indicating Watchdog Reset).

Could someone tell me if this is expected behavior or do I have some issue? Is there any limitations when debugging with the watchdog turned on for a multicore project? If someone could provide some advice here I would greatly appreciate it; specifically what are the best practices for debugging multicore MCUs with watchdogs.

When I run without any breakpoints (or with the debugger not attached) everything works as expected.

I am planning to also utilize WDOG1 to have the M0+ core responsible for kicking it.

Any insight would be great; also, if anything is unclear please let me know and I can provide additional info.

Thanks!

0 项奖励
0 回复数