From my customer:
Question: Is the R/W# signal guaranteed to be held low through all of S5 during a write cycle? Section 5.4.2 "Write Cycles" in the MC68332 SIM (System Integration Module) Reference Manual gives a description of a write operation. Figure 5-5 shows the logic levels of various control signals through states (S0 - S5) of a write cycle. The description says "R/W# remains valid throughout S5", and Figure 5-5 also indicates this. However, Figure A-5 and Table A-6 in Appendix A give detailed timing information for the R/W# signal during a write cycle. Timing specfication #17 (tSNRN) states "AS#, DS#, CS# Negated to R/W# High" is a minimum of 15ns. I interpret this to mean that R/W# could transition low-to-high as soon as 15ns after CS# is negated. CS# is negated at the end of S4/beginning of S5. Specification #12 (tCLSN) states CS# can take 2 to 29 ns to negate after the clock goes low at the end of S4. Combining spec #17 and #12, this means the R/W# signal could go low-to-high as soon as 17ns after the beginning of S5. For a 16MHz system clock (62.5ns period, 31.25ns half-period), this means R/W# could transition high about halfway through S5. Thus, there is a contradiction between what is stated in Section 5.4.2 and the timing specifications given in Table A-6 of Appendix A. Should I go with what Section 5.4.2 says or with what Table A-6 says? Am I interpreting the spec in Table A-6 correctly? Again, my ultimate question is: Will R/W# be held low throughout the state S5 during a write cycle? Reason for question: I am asking because we are replacing obsolete 5V Flash memory on a 20 year old product with new 3.3V Flash. We are adding a level shifting transceiver to shift data signals between 5V and 3.3V to accommodate this "new" Flash. I would like to use the R/W# signal to control the direction of this transceiver, but if R/W# is not held low all the way to the end of a write cycle (i.e. through the end of S5), it will cause bus contention problems and I will need to use something else in the design. This is still in the design phase so we have no measurements to take. However, I could go in and take measurements on the old product as you suggested. Our full part number is MC68332ACEH25. The SIM manual I am referencing is located here: http://www.nxp.com/files/microcontrollers/doc/ref_manual/SIMRM.pdf?fasp=1&WT_TYPE=Reference%20Manual...
The critical timing is Tchdh. To guarantee no bus contention, the CPU drivers have to deassert before the bus buffer is enabled.
Is the FLASH the only device on the external bus? You would normally use Chip Select gated with R/W to drive bus buffers, and only drive inwards on Read AND Chip Select.
Watch out for Interrupts. They run a "CPU Space Cycle" on the external bus. If you have the external buffer defaulting to driving the bus when there isn't a Write Cycle then this might cause problems.
Find the sentence in the SIM chapter that says "If multiple chip-selects are to be used to provide control signals to a single device...". You can program multiple chip-selects to assert simultaneously as different control signals for the same transfer. You might be able to program a spare chip-select or two to generate the buffer control signals.
In general, the bus interface is synchronous. Signals transition after the clock edges in the diagrams. The timing values that you are looking at that seem to be contradictory are the "worst case delay buildup" with the first signal running late and the second signal running early at worst-case capacitive loads and so on.
These chips have been used in designs where there are more memory chips than the CPU can driver on its own, therefore requiring external bus buffering. It would be worth trying to find the schematics of any development board designed like this to see how they handled the external bus buffering logic.
Look at Figure 1 on this diagram. I'm asking "why are they tying CS and RW into that gate?". Answering that might help with your question.
Address will become deasserted at or after the rising edge of S5. It will not become invalid before this. AS, DS and CS will be deasserted before the end of S5.