MCF5235 bdm documentation


MCF5235 bdm documentation

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Contributor I

I am currently working on better patch to support the coldfire 2/2M processors with the m68k-bdm [1]. Working on that project I found the following information in the manuals:

Coldfire 2/2M Users Manual: 7-22, page 159:
Control Register Map for Read Control Register (RCREG) command:
RAMBAR0 = $C04

MCF5235 Manual: 3-8, page 697:
Control Register Map for Read Control Register (RCREG) command:

From testing I known that the second value is correct but I am still wondering why it was chosen this way. Does that mean that a debugger can't treat all Coldfire 2 cores in the same way? I wanted to make only a distinction between 2 and 2M cores (the later one having the MAC registers).

Christian Walter


Message Edited by wolti on 05-06-200604:00 PM

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NXP Employee
NXP Employee

Hi Christian,

The ColdFire 2/2M is very old documenation and the MCF5235 documenation is much newer.

The RAMBAR address did change from older to newer versions (it keeps the chip designers busy!). 

Regards, DavidS

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