We started to explore the MCF51JM128 in the 44 LQFP package in a first design. First steps with this familiy we did with the DEMOJM Evaluation Board which comes with a MCF51JM128 module in the 64 LQFP package. By testing our design with the 44 LQFP package we saw, that the clock circuit (6MHz Crystal, 22pF, with and/or without Rf=1MOhm & Rs=10Ohm) did not work at all. Additionnally the RESET pin delivered a perfect about 20kHZ square wave which we didn't get away even with 10kOhm Pullup and 100nF Pulldown as recommended in the referende manual. We tested it with a new chip, same results. Then again with a new chip we build a flying circuit with VSS(5V),VDD,RESET(10k/100nF) and BKGD(10k pullup) connected and a crystal clock circuit on EXTAL/XTAL as described above. Same results, the EXTAL/XTAL pins showed a pure ground line on the oscilloscope. Then we cutted our flying circuit from the 44 LQFP package and connected it to the 64LQFP module from our DEMOJM evaluation board. Result: It works!, no more square wave out of the RESET pin and a clear clock at the XTAL pins. So our question is: Do we have 3 defect chip (new samples from our distributor) or is the pinout for the 44 LQFP package given in the datasheet
Document Number: MCF51JM128
Rev. 2, 09/2008
Thanks in advance for any help as otherwise we have to bury this chip.
Did anyone find an explanation for this behaviour ?
I have the same on my board which was working before.
Something is now broken but I don't understand what.
I swapped the coldfire with a new one and same result.
The clock circuit (8MHz Crystal, 15pF, with and/or without Rf=1MOhm) did not work at all. Additionnally the RESET pin delivered a perfect about 20kHZ square wave which we didn't get away even with 10kOhm Pullup and 100nF Pulldown as recommended in the referende manual.
According to referencee manual, default MCG mode is FLL engaged internal, so external oscilator should be off. Did you flash your chips with software that enables external oscilator?
/RESET pin is bidirectional. From manual: "When any reset is initiated (whether from an external source or from an internal source, the RESET pin is driven low for approximately 66 bus cycles and released." I didn't try JM yet and not sure if these 66 bus cycles in FEI mode could explain 20kHz or not, but do you have any software in your chip? If chip is blank, then COP and/or illegal address/opcode resets could keep resetting your chip and make some oscilations on /RESET pin.