T1024 DDR3 SODIMM issue

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T1024 DDR3 SODIMM issue

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sureshk
Contributor II

Hi guys,

My custom board which is based on T1024, has DDR3L module MT4KTF25664HZ-1G9P1 (CL13, 1.35V, CLK:1.07NS/1866MT/S).  Before we were using MT4KTF25664HZ-1G6E1 (CL11, 1600MT/s) in our design and working properly  with below register configuration.

  

{1,  833,  4, 4,6, 0x06060607, 0x07080800},   

     {1,  833,  0, 4,6, 0x06060607, 0x07080800},  

     {1,  1350, 4, 4,7, 0x07070708, 0x08080800},   

     {1,  1350, 0, 4,7, 0x07070708, 0x08080800},  

     {1,  1066, 4, 4,7, 0x06060708, 0x07080800},   

     {1,  1066, 0, 4,7, 0x06060708, 0x07080800},

     {1,  1666, 4, 4,7, 0x06070809, 0x080A0A00},   

     {1,  1666, 0, 4,7, 0x06070809, 0x080A0A00},

After chaging the DDR module to MT4KTF25664HZ-1G9P1 , most of the times  UBOOT stopping at DDR..

Kindly help us in changes to be done in above registers to work with CL13 DDR module..

Below attached the DDR module datasheet..

Thyank you..

Regards,

  suresh

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yipingwang
NXP TechSupport
NXP TechSupport

Hello suresh k,

We suggest you use DDRv tool to do optimize and validate DDR controller configuration parameters on the target board, especially for wrlvl start, wrlvl ctl2 and wrlvl ctl3 parameters.

Please create a QCVS tool according your DDR data sheet or using read from SPD from the target, then use DDRv tool to do Centering the clock and Read/Write ODT and driver validation to optimize DDR controller configuration in a dynamic way.

Please refer to DDRv user manual http://www.nxp.com/docs/en/user-guide/QCVS_DDR_User_Guide.pdf .

Please download DDRv tool from CodeWarrior Networked Applications: DDRV|NXP , it is installed on top of QCVS tool, and requires a specific license, if you don't have the "Specialist level" license, please use the 30 days evaluation license first.


Have a great day,
TIC

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