calculating proper BAUD and BUSCLK

[irob]

So I'm confused.  I found this thread which only confirms my confusion.  I'm using a 9S08QE32 (though this question applies to quite a few chips in the S08 family.

Page 21-22 of the QE32 reference manual states:

ICSOUT — This clock source is used as the CPU clock and is divided by two to generate the
peripheral bus clock, BUSCLK.

I have the FLL selected as my ICS, so therefore my rate is 8.372 MHz.  Further, my BUSCLK would be 4.186 MHz, right?

For my SCI port, page 222-223 says the BAUD is calculated with:

BAUD = BUSCLK / (SBR[12:0] * 16)

Or written a different way:

SBR = BUSCLK / (16 * BAUD)

But my baud calculations are off.  It's as if the BUSCLK is off by that factor of two.  If I set my BAUD to 9600, the serial port actually is working at 19200.  2x error.

What am I missing here?

[bigmac]

Hello irob,

Without knowing your actual register settings, it is not possible to see the precise problem.

The formula for the bus frequency would be as follows -

For ICSSC_DRS = 0,

fbus = fref * 512 / 2 / Bdiv

For ICSSC_DRS = 1,

fbus = fref * 1024 / 2 / Bdiv

The Bdiv factor will be determined by the setting of ICSC2_BDIV.

Assuming ICSSC_DRS = 0, to obtain a bus frequency of 4.186MHz would requre the reference frequency to be trimmed to 32.703 kHz, and would also require a Bdiv divisor value of 2.  If ICSSC_DRS = 1, the Bdiv divisor would need to be increased to 4.

The nearest SBR divider value for 9600 bits per second would be 27.  However, there will be a baud error of nearly 1 percent.  Other trim settings (and bus frequencies) will result in exact baud rates.  For bus frequencies within the range 4 to 5 MHz, consider the following possible settings -

SBR  fref(kHz)  fbus

26   31.25      4.000

27   32.40      4.147

28   33.60      4.301

29   34.80      4.454

30   36.00      4.608

31   37.20      4.762

32   38.40      4.915

Regards,

Mac

[irob]

bigmac, you continue to be a valued Freescale resource on these fora!

Yet I was pouring over your formulae and can't seem to find exactly where in the QE datasheet where they are referenced quite like you've paraphrased.  Can you cite a page number for your fbus formula?

The baud formula on page 211 is pretty clear.  Th eonly unknown is BUSCLK and the SBR word.

Also, I'm confused by how you are tying SBR to to baud rate in your table.  Using your fbus formula, I can't get any of the numbers you list in the table, solving for either SBR or fbus.

It would seem to me that assuming default register values for the FLL on power up, the datasheet formula for baud on pg 211 is more than enough to solve.  The question is just knowing what BUSCLK is.

My full ICS register settings:

  ICSC1_CLKS = 0b00;      // use FLL  ICSC1_IREFS = 1;        // Internal reference clock selected.  ICSC1_IRCLKEN = 1;      // ICSIRCLK active.  ICSC1_IREFSTEN = 0;     // Internal reference clock is disabled in stop.   ICSC2_BDIV = 0b00;      // Divides selected clock by 1.  ICSSC_IREFST = 0;       // source of reference clock is external clock.  ICSSC_CLKST = 0b00;     // output of FLL is selected

Throroughly confused

[bigmac · Accepted solution]

Hello irob,

The formulae for calculating the bus frequency were derived from data given at a number of locations within the Reference Manual.  The primary reference is Tables 11.6 and 11.7 that indicate a number of different DCO ranges, and the FLL factor associated with each range.  The low and mid ranges would be mostly of interest.  It is appropriate for the internal reference use, that ICSSC_DMX32 = 0.

From Table 11.7, you can deduce that 

DCO_freq = fref * FLL_factor 

Then from Fig. 11.2 block diagram it can be observed that, when FLL output is selected,

ICSOUT_freq = DCO_freq / Bdiv

where Bdiv = 1, 2, 4 or 8, determined by ICSC2_BDIV setting

Further reference to section 1.3 and Fig. 1.2, show a further divide by 2 stage, so that

BUSCLK = ICSOUT_freq / 2

Combining these expressions will result in the previous formulae.  For yur current register settings that use low range by default, the FLL factor will be 512, and Bdiv is 1, giving

BUSCLK = fref * 512 / 1 / 2 = fref * 256

Since fref will be trimmed somewhere within the range 31.25 to 39.0625 kHz, the bus frequency will have the range 8.000 MHz to 10.000 MHz, double the frequency that you were anticipating.  If you were to trim the reference frequency for 32.703 kHz, as was previously implied, the actual bus frequency would be 8.372 MHz.  For 9600 bits per second, the SBR setting would need to be 54 or 55, for a baud error of about 1 percent.

With the code lines,

  ICSSC_IREFST = 0;       // source of reference clock is external clock.
  ICSSC_CLKST = 0b00;     // output of FLL is selected

these will not do anything since you are attempting to write to read-only status bits.  However, you should explicitly set the DRS and DMX32 bits, rather than relying on the POR default. ICSSC = 0; would be more appropriate for ICS initialisation.

Regards,

Mac

[irob]

Well, shoot, now that I'm getting into the meat of your answer, there's one step I don't follow still.

bigmac wrote:

Since fref will be trimmed somewhere within the range 31.25 to 39.0625 kHz, the bus frequency will have the range 8.000 MHz to 10.000 MHz, double the frequency that you were anticipating.

Says who/where?  I can't find this relationship between bus frequency (is this BUSCLK?) and DCO.

[irob]

Wow, bigmac, what can I say?  Impeccable contributions you make.  I've bookmarked this little nugget.