Hello Johan.
Interresting what you say regarding the FACCERR & FPVIOL bits. I was under the impression that these bits were set only after the command was registered by writing to the FCBEF bit.
I look at the SpSub code (reproduced below, this code is from the reference manual & monitor program), and the FCBEF bit is set by a STA instruction which would overwrite all other bits in FSTAT.
When the program returns to DoOnStack A is shifted left 1 bit which would normally put FPVIOL & FACCERR at bits 7 & 6 repectively. If what you say is true, then a check for these error flags should be done immediately after storing the data to the flash address (sta ,x).
Can anyone confirm or deny this?
JC
;********************************************************************************
;* SpSub - This variation of SpSub performs all of the steps for
;* programming or erasing flash from RAM. SpSub is copied onto the
;* stack, SP is copied to H:X, and then the copy of SpSub in RAM is
;* called using a JSR 0,X instruction.
;*
;* At the time SpSub is called, the data to be programmed (dummy data
;* for an erase command), is in A and the flash address is on the
;* stack above SpSub. After return, PVIOL and ACCERR flags are in bits
;* 6 and 5 of A. If A is shifted left by one bit after return, it
;* should be zero unless there was a flash error.
;*
;* Uses 24 bytes on stack + 2 bytes if a BSR/JSR calls it
;********************************************************************************
SpSub: ldhx <SpSubSize+4,sp ;get flash address from stack
sta ,x ;write to flash; latch addr and data
lda SpSubSize+3,sp ;get flash command
sta FCMD ;write the flash command
lda #mFCBEF ;mask to initiate command
sta FSTAT ;[pwpp] register command
nop ;[p] want min 4~ from w cycle to r
ChkDone: lda FSTAT ;[prpp] so FCCF is valid
lsla ;FCCF now in MSB
bpl ChkDone ;loop if FCCF = 0
SpSubEnd: rts ;back into DoOnStack in flash
SpSubSize: equ (*-SpSub)
;********************************************************************************