####################################### #FILE # $RCSfile: ep8248_init.cfg,v $ # $Date: 2007/12/18 11:39:50 $ # $Revision: 1.2 $ #DESCRIPTION # Initialization file for # the Embedded Planet EP_8248 board #COPYRIGHT # (c) 2003 Freescale Corporation # All rights reserved. #HISTORY # $Log: ep8248_init.cfg,v $ # Revision 1.2 2007/12/18 11:39:50 r04474 # update # # Revision 1.1 2004/11/15 14:02:19 c-dnegrea # files moved from Initialization_Files/JTAG to Initialization_Files/PQ2 # # Revision 1.1 2004/06/17 16:06:34 mposirca # initial revision # ######################################## # memory map # # 16MB sdram 0x0000_0000 - 0x00FF_FFFF # 1MB bcsr 0xFA0_00000 - 0xFA0F_FFFF # 8MB flash 0xFF80_0000 - 0xFFFF_FFFF # 256KB + 128KB internal memory 0x0470_0000 0x0476_0000 # IMMR assumed to be at 0x00000000 due to hw config word # Set the IMMR so the debugger plugin knows where it is since # the IMMR itself is a memory mapped register. This does not # actually write anything to the target, it is simply to inform # the debugger plugin where the IMMR is, writing SPR311 (MBAR) register #setMMRBaseAddr 0x00000000 writereg MBAR 0x00000000 # move internal memory base address at 0x04700000 writemmr IMMR 0xF0000000 #setMMRBaseAddr 0x04700000 writereg MBAR 0xF0000000 # SYPCR: turn off watchdog timer writemmr SYPCR 0xffffff83 writemmr SCCR 0x000001B1 writemmr RMR 0x00000000 # RMR=1: Set checkstop reset enable in the Reset Mode Register writemmr BCR 0x00000000 writemmr SIUMCR 0x4224C200 # Setup the chip selects # CS0 is 8MB flash at 0xff800000, 32-bit port, no error checking, writable, GPCM, 60x bus, valid writemmr BR0 0xff001001 writemmr OR0 0xff000c42 # CS2 is board control & status registers at 0xFA000000, 8-bit port size, GPCM writemmr OR2 0xffff0ca2 writemmr BR2 0xf0200801 # CS1 is 16MB SDRAM at 0x00000000, 32-bit port size, SDRAM machine, r/w, valid writemmr OR1 0xff000c42 writemmr BR1 0xfe001001 writemmr PSRT 0x0E writemmr MPTPR 0x3100 # MPTPR: Set the Memory Periodic Timer Prescaler sleep 100 # precharge all banks writemmr PSDMR 0x834D1252 writemem.b 0x00000110 0x00 # cbr refresh writemmr PSDMR 0x826b36a3 writemmr PSDMR 0xaa66b72e writemem.b 0x00000110 0xFF writemem.b 0x00000110 0xFF writemem.b 0x00000110 0xFF writemem.b 0x00000110 0xFF writemem.b 0x00000110 0xFF writemem.b 0x00000110 0xFF writemem.b 0x00000110 0xFF writemem.b 0x00000110 0xFF ; Issue Mode register write writemmr PSDMR 0x9a66b72e writemem.b 0x00000110 0x00 writemmr PSDMR 0xc266b72e writemmr TESCR1 0x00004000 writemmr TESCR2 0x00000000 # SEC configuration # program SEC Mask Register with value 0xFFFE0000 - 128 KB memory space writemem.l 0x047101BC 0xFFFE0000 #SECMR # program SEC Base Register - IMMR + 0x40000 writemem.l 0x047101B4 0x04740001 #SECBR writereg MSR 0x00003002