########################### PN7160 libnfc-nxp.conf ############################ ############################################################################### # Logging Levels. Suggested value for debugging is 0x03. # NXPLOG_GLOBAL_LOGLEVEL - Configuration for Global logging level # NXPLOG_EXTNS_LOGLEVEL - Configuration for extns logging level # NXPLOG_NCIHAL_LOGLEVEL - Configuration for enabling logging of HAL # NXPLOG_NCIX_LOGLEVEL - Configuration for enabling logging of NCI TX packets # NXPLOG_NCIR_LOGLEVEL - Configuration for enabling logging of NCI RX packets # NXPLOG_FWDNLD_LOGLEVEL - Configuration for enabling logging of FW download functionality # NXPLOG_TML_LOGLEVEL - Configuration for enabling logging of TML # Logging Levels # NXPLOG_DEFAULT_LOGLEVEL 0x01 # NXPLOG_DEBUG_LOGLEVEL 0x03 # NXPLOG_WARN_LOGLEVEL 0x02 # NXPLOG_ERROR_LOGLEVEL 0x01 # NXPLOG_SILENT_LOGLEVEL 0x00 NXPLOG_EXTNS_LOGLEVEL=0x03 NXPLOG_NCIHAL_LOGLEVEL=0x03 NXPLOG_NCIX_LOGLEVEL=0x03 NXPLOG_NCIR_LOGLEVEL=0x03 NXPLOG_FWDNLD_LOGLEVEL=0x03 NXPLOG_TML_LOGLEVEL=0x03 ############################################################################### # TRANSPORT Type # 0x00 - I2C /SPI for noraml nxpnfc driver # 0x01 - Not Used, kept to align with Android code # 0x02 - ALT_I2C # 0x03 - ALT_SPI NXP_TRANSPORT=0x00 ############################################################################### # Nfc Device Node name NXP_NFC_DEV_NODE="/dev/nxpnfc" ############################################################################### # Extension for Mifare reader enable MIFARE_READER_ENABLE=0x01 ############################################################################### # Firmware file type #.so file 0x01 #.bin file 0x02 NXP_FW_TYPE=0x01 ############################################################################### # System clock source selection configuration #define CLK_SRC_XTAL 1 #define CLK_SRC_PLL 2 NXP_SYS_CLK_SRC_SEL=0x01 ############################################################################### # Dynamic RSSI feature enable # Disable 0x00 # Enable 0x01 NXP_AGC_DEBUG_ENABLE=0x00 ############################################################################### # NXP proprietary settings NXP_ACT_PROP_EXTN={2F, 02, 00} ############################################################################### # NFC forum profile settings NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00} ############################################################################### # To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set # to 0x00 NXP_I2C_FRAGMENTATION_ENABLED=0x00 ############################################################################### # System clock frequency selection configuration #define CLK_FREQ_13MHZ 1 #define CLK_FREQ_19_2MHZ 2 #define CLK_FREQ_24MHZ 3 #define CLK_FREQ_26MHZ 4 #define CLK_FREQ_38_4MHZ 5 #define CLK_FREQ_52MHZ 6 NXP_SYS_CLK_FREQ_SEL=0x00 ############################################################################### # The timeout value to be used for clock request acknowledgment # min value = 0x01 to max = 0x06 NXP_SYS_CLOCK_TO_CFG=0x06 ############################################################################### # TVDD configurations settings # Allow NFCC to configure External TVDD # There are two possible configurations (0x01 or 0x02): # CFG1: Vbat is used to generate the VDD(TX) through TXLDO # CFG2: external 5V is used to generate the VDD(TX) through TXLDO NXP_EXT_TVDD_CFG=0x02 # CFG1: 3.3V for both Reader and Card modes #NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01, 00, D0, 0C} #NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, 01, 01, 00, 00, 00, 00, 00, 10, 0C} NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, 01, 01, 00, 00, 00, 29, 00, D0, 0C} # CFG2: VBAT2 to 5V and 4.7V for both Reader and Card modes NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, 02, B2, 00, B2, 1E, 99, 00, 10, 0C} ############################################################################### # Core configuration settings NXP_CORE_CONF={ 20, 02, 31, 0F, 85, 01, 01, 28, 01, 00, 21, 01, 00, 30, 01, 08, 31, 01, 03, 32, 01, 60, 38, 01, 01, 33, 04, 01, 02, 03, 04, 54, 01, 06, 50, 01, 02, 5B, 01, 00, 80, 01, 01, 81, 01, 01, 82, 01, 0E, 18, 01, 01 } ############################################################################### # NXP Proprietary core configuration extensions # For more details refer to the NFC Controller User Manual NXP_CORE_CONF_EXTN={20, 02, 09, 02, A0, 5E, 01, 01, A0, 40, 01, 01 } ############################################################################### # RF configuration settings # Below settings relates to OM5578 demo kit RF performance optimization #NXP_RF_CONF_BLK_1={ 20, 02, A3, 13, # A0, 0D, 06, 04, 35, 90, 01, F4, 01, # A0, 0D, 06, 06, 44, 01, 90, 03, 00, # A0, 0D, 06, 06, 30, B0, 01, 10, 00, # A0, 0D, 06, 06, 42, 02, 00, FF, FF, # A0, 0D, 03, 06, 3F, 04, # A0, 0D, 06, 20, 42, 88, 00, FF, FF, # A0, 0D, 04, 22, 44, 22, 00, # A0, 0D, 06, 22, 2D, 50, 34, 0C, 00, # A0, 0D, 06, 32, 42, F8, 00, FF, FF, # A0, 0D, 06, 34, 2D, 24, 37, 0C, 00, # A0, 0D, 06, 34, 33, 86, 80, 00, 70, # A0, 0D, 04, 34, 44, 22, 00, # A0, 0D, 06, 42, 2D, 15, 45, 0D, 00, # A0, 0D, 04, 46, 44, 22, 00, # A0, 0D, 06, 46, 2D, 05, 59, 0E, 00, # A0, 0D, 06, 44, 42, 88, 00, FF, FF, # A0, 0D, 06, 56, 2D, 05, 9F, 0C, 00, # A0, 0D, 06, 54, 42, 88, 00, FF, FF, # A0, 0D, 06, 0A, 33, 80, 86, 00, 70 #} ############################################################################### # RF configuration settings # Below settings relates to OM27160 eval kit RF performance optimization # This section needs to be updated with the correct values based on the platform NXP_RF_CONF_BLK_1={ 20, 02, 4C, 09, A0, 0D, 03, 78, 0D, 02, A0, 0D, 03, 78, 14, 02, A0, 0D, 06, 4C, 44, 65, 09, 00, 00, A0, 0D, 06, 4C, 2D, 05, 35, 1E, 01, A0, 0D, 06, 82, 4A, 55, 07, 00, 07, A0, 0D, 06, 44, 44, 03, 04, C4, 00, A0, 0D, 06, 46, 30, 50, 00, 18, 00, A0, 0D, 06, 48, 30, 50, 00, 18, 00, A0, 0D, 06, 4A, 30, 50, 00, 08, 00 } ############################################################################### # NFCLD ON-Threshold set to 300mA/m # RSSI Rext Register # DLMA CTRL Register # Below settings relates to OM27160 eval kit RF performance optimization # This section needs to be updated with the correct values based on the platform NXP_RF_CONF_BLK_2={ 20, 02, 1E, 03, A0, 38, 04, 24, 10, 0B, 00, A0, AA, 04, 38, 04, 98, 08, A0, AF, 0C, 83, D5, 78, 80, 00, 83, D5, 78, 80, 00, 77, 08 } ############################################################################### # DPC_SETTINGS for 180mA Target Current # Below settings relates to OM27160 eval kit RF performance optimization # This section needs to be updated with the correct values based on the platform NXP_RF_CONF_BLK_3={ 20, 02, 5B, 01, A0, 0B, 57, F1, 91, 90, 50, 0F, 4E, 00, 4B, 15, B7, AA, 4B, 1F, A7, 99, 61, 9F, 97, 99, 6C, 9F, 97, 99, 6F, 9F, 97, 99, 7A, 9F, 97, 00, 7C, 9F, 07, 00, 87, 1F, 07, 00, 8C, 9F, 07, 00, 94, 9F, 07, 00, 97, 9F, 07, 00, A2, 9F, 04, 00, A4, 9F, 04, 00, AF, 9F, 04, 00, B1, 9F, 04, 00, BC, 9F, 02, 00, C5, 9F, 00, 00, CC, 9F, 00, 00, D7, 1F, 00, 00, E2, 1F, 00, 00 } ############################################################################### # APC RSSI Table Configuration # Below settings relates to OM27160 eval kit RF performance optimization # This section needs to be updated with the correct values based on the platform NXP_RF_CONF_BLK_4={ 20, 02, 98, 01, A0, 34, 94, 23, 04, 18, CB, 00, 00, 59, 01, 00, D9, 01, 00, 44, 02, 00, A5, 02, 00, 78, 03, 00, 45, 04, 00, 20, 05, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 18, CB, 00, 00, 59, 01, 00, D9, 01, 00, 44, 02, 00, A5, 02, 00, 78, 03, 00, 45, 04, 00, 20, 05, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00, 77, 06, 00 } ############################################################################### # NXP RF configuration APC TX Table Configuration # Below settings relates to OM27160 eval kit RF performance optimization # This section needs to be updated with the correct values based on the platform NXP_RF_CONF_BLK_5={ 20, 02, A4, 01, A0, A9, A0, 00, C1, 00, 0A, 01, 80, 41, 0A, 02, 81, 83, 0A, 03, C0, 42, 06, 04, 80, 46, 06, 05, C3, 01, 03, 06, C2, 05, 03, 07, C2, 4A, 03, 08, 41, 00, 0A, 08, C0, D4, 06, 08, C3, 8B, 03, 09, 01, 82, 0A, 09, C3, 92, 03, 0A, 40, 02, 06, 0A, C4, CC, 03, 0B, 00, 06, 06, 0B, 40, D4, 03, 0C, 44, 00, 03, 0D, 42, 04, 03, 0E, 42, 48, 03, 0F, 43, 50, 03, 10, 43, 91, 03, 11, 44, 95, 03, 12, 46, 8E, 01, 13, 47, C4, 01, 14, 48, CA, 01, 15, 49, D0, 01, 16, 4B, D4, 01, 17, 4D, D6, 01, 18, 49, 72, 03, 19, 4E, 68, 01, 1A, 52, 70, 01, 1B, 53, 74, 01, 1C, 54, B4, 01, 1D, 52, EA, 01, 1E, 53, F0, 01, 1F, 53, F0, 00, 1F, 53, F0, 00, 1F, 53, F0, 00, 1F, 53, F0, 00 } ############################################################################### # Extended APDU length for ISO_DEP ISO_DEP_MAX_TRANSCEIVE=0xFEFF ############################################################################### # Choose the presence-check algorithm for type-4 tag. If not defined, the default value is 1. # 0 NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm # 1 NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block # 2 NFA_RW_PRES_CHK_ISO_DEP_NAK; ISO-DEP protocol's nak presence check command PRESENCE_CHECK_ALGORITHM=2 ############################################################################### #T4T NFCEE ENABLE #bit pos 0 = Enable T4T NFCEE from NFCC (Only wired R/W activated, RF read only activated) NXP_T4T_NFCEE_ENABLE=0x01 ############################################################################### #Set the T4TNfcee AID Power state : #This settings will be used when application does not set this parameter # bit pos 0 = Switch On # bit pos 1 = Switch Off # bit pos 2 = Battery Off # bit pos 3 = Screen off unlock # bit pos 4 = Screen On lock # bit pos 5 = Screen Off lock DEFAULT_T4TNFCEE_AID_POWER_STATE=0x3B ###############################################################################