/***********************************************************************************************************************
 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
 **********************************************************************************************************************/
/*
 * How to set up clock using clock driver functions:
 *
 * 1. Setup clock sources.
 *
 * 2. Set up wait states of the flash.
 *
 * 3. Set up all dividers.
 *
 * 4. Set up all selectors to provide selected clocks.
 */

/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v12.0
processor: LPC55S69
package_id: LPC55S69JBD100
mcu_data: ksdk2_0
processor_version: 14.0.0
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */

#include "fsl_power.h"
#include "fsl_clock.h"
#include "clock_config.h"

/*******************************************************************************
 * Definitions
 ******************************************************************************/

/*******************************************************************************
 * Variables
 ******************************************************************************/

/*******************************************************************************
 ************************ BOARD_InitBootClocks function ************************
 ******************************************************************************/
void BOARD_InitBootClocks(void)
{
    BOARD_BootClockPLL100M();
}

/*******************************************************************************
 ******************** Configuration BOARD_BootClockFRO12M **********************
 ******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFRO12M
outputs:
- {id: System_clock.outFreq, value: 12 MHz}
settings:
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
sources:
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */

/*******************************************************************************
 * Variables for BOARD_BootClockFRO12M configuration
 ******************************************************************************/
/*******************************************************************************
 * Code for BOARD_BootClockFRO12M configuration
 ******************************************************************************/
void BOARD_BootClockFRO12M(void)
{
#ifndef SDK_SECONDARY_CORE
    /*!< Set up the clock sources */
    /*!< Configure FRO192M */
    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */

    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */

    POWER_SetVoltageForFreq(12000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
    CLOCK_SetFLASHAccessCyclesForFreq(12000000U);          /*!< Set FLASH wait states for core */

    /*!< Set up dividers */
    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */

    /*!< Set up clock selectors - Attach clocks to the peripheries */
    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO12M */

    /*!< Set SystemCoreClock variable. */
    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
#endif
}

/*******************************************************************************
 ******************* Configuration BOARD_BootClockFROHF96M *********************
 ******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockFROHF96M
outputs:
- {id: System_clock.outFreq, value: 96 MHz}
settings:
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
sources:
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */

/*******************************************************************************
 * Variables for BOARD_BootClockFROHF96M configuration
 ******************************************************************************/
/*******************************************************************************
 * Code for BOARD_BootClockFROHF96M configuration
 ******************************************************************************/
void BOARD_BootClockFROHF96M(void)
{
#ifndef SDK_SECONDARY_CORE
    /*!< Set up the clock sources */
    /*!< Configure FRO192M */
    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */

    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */

    POWER_SetVoltageForFreq(96000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
    CLOCK_SetFLASHAccessCyclesForFreq(96000000U);          /*!< Set FLASH wait states for core */

    /*!< Set up dividers */
    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */

    /*!< Set up clock selectors - Attach clocks to the peripheries */
    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to FRO_HF */

    /*!< Set SystemCoreClock variable. */
    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
#endif
}

/*******************************************************************************
 ******************** Configuration BOARD_BootClockPLL100M *********************
 ******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockPLL100M
called_from_default_init: true
outputs:
- {id: FXCOM1_clock.outFreq, value: 48 MHz, locked: true, accuracy: '0.001'}
- {id: FXCOM2_clock.outFreq, value: 48 MHz, locked: true, accuracy: '0.001'}
- {id: FXCOM3_clock.outFreq, value: 48 MHz, locked: true, accuracy: '0.001'}
- {id: FXCOM4_clock.outFreq, value: 48 MHz, locked: true, accuracy: '0.001'}
- {id: FXCOM5_clock.outFreq, value: 48 MHz, locked: true, accuracy: '0.001'}
- {id: FXCOM6_clock.outFreq, value: 48 MHz, locked: true, accuracy: '0.001'}
- {id: FXCOM7_clock.outFreq, value: 48 MHz, locked: true, accuracy: '0.001'}
- {id: System_clock.outFreq, value: 100 MHz, locked: true, accuracy: '0.001'}
- {id: TRACE_clock.outFreq, value: 100.1 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
- {id: WDT_clock.outFreq, value: 1 MHz}
settings:
- {id: PLL0_Mode, value: Normal}
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
- {id: ENABLE_CLKIN_ENA, value: Enabled}
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
- {id: SYSCON.FCCLKSEL1.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FCCLKSEL2.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FCCLKSEL3.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FCCLKSEL4.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FCCLKSEL5.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FCCLKSEL6.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FCCLKSEL7.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FRGCTRL1_DIV.scale, value: '267'}
- {id: SYSCON.FRGCTRL2_DIV.scale, value: '267'}
- {id: SYSCON.FRGCTRL3_DIV.scale, value: '267'}
- {id: SYSCON.FRGCTRL4_DIV.scale, value: '267'}
- {id: SYSCON.FRGCTRL5_DIV.scale, value: '267'}
- {id: SYSCON.FRGCTRL6_DIV.scale, value: '267'}
- {id: SYSCON.FRGCTRL7_DIV.scale, value: '267'}
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
- {id: SYSCON.PLL0DIV.scale, value: '2'}
- {id: SYSCON.PLL0M_MULT.scale, value: '1001'}
- {id: SYSCON.PLL0N_DIV.scale, value: '40'}
- {id: SYSCON.TRACECLKSEL.sel, value: SYSCON.TRACECLKDIV}
- {id: SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_CFG, value: Enabled}
- {id: UTICK_EN_CFG, value: Enable}
sources:
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
- {id: SYSCON.fro_1m.outFreq, value: 1 MHz}
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */

/*******************************************************************************
 * Variables for BOARD_BootClockPLL100M configuration
 ******************************************************************************/
/*******************************************************************************
 * Code for BOARD_BootClockPLL100M configuration
 ******************************************************************************/
void BOARD_BootClockPLL100M(void)
{
#ifndef SDK_SECONDARY_CORE
    /*!< Set up the clock sources */
    /*!< Configure FRO192M */
    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */

    /*!< Configure fro_1m */
    SYSCON->CLOCK_CTRL |=  SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK;                 /*!< Ensure fro_1m is on */

    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */

    /*!< Configure XTAL32M */
    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */

    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK;               /* The FRO 1 MHz clock to UTICK is enabled. */

    POWER_SetVoltageForFreq(100100000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
    CLOCK_SetFLASHAccessCyclesForFreq(100100000U);          /*!< Set FLASH wait states for core */

    /*!< Set up PLL */
    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
    const pll_setup_t pll0Setup = {
        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(7U) | SYSCON_PLL0CTRL_SELP(31U),
        .pllndec = SYSCON_PLL0NDEC_NDIV(40U),
        .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(1001U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
        .pllRate = 100100000U,
        .flags =  PLL_SETUPFLAG_WAITLOCK
    };
    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */

    /*!< Set up dividers */
    CLOCK_SetClkDiv(kCLOCK_DivArmTrClkDiv, 0U, true);               /*!< Reset TRACECLKDIV divider counter and halt it */
    CLOCK_SetClkDiv(kCLOCK_DivArmTrClkDiv, 1U, false);              /*!< Set TRACECLKDIV divider to value 1 */
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg1, 11U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg1, 3072U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #endif
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg2, 11U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg2, 3072U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #endif
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg3, 11U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg3, 3072U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #endif
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg4, 11U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg4, 3072U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #endif
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg5, 11U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg5, 3072U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #endif
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg6, 11U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg6, 3072U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #endif
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg7, 11U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg7, 3072U, false);         /*!< Set DIV to value 0xFF and MULT to value 11U in related FLEXFRGCTRL register */
    #endif
    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
    CLOCK_SetClkDiv(kCLOCK_DivWdtClk, 0U, true);               /*!< Reset WDTCLKDIV divider counter and halt it */
    CLOCK_SetClkDiv(kCLOCK_DivWdtClk, 1U, false);         /*!< Set WDTCLKDIV divider to value 1 */
    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true);               /*!< Reset PLL0DIV divider counter and halt it */
    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false);         /*!< Set PLL0DIV divider to value 2 */

    /*!< Set up clock selectors - Attach clocks to the peripheries */
    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM1);                 /*!< Switch FLEXCOMM1 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM2);                 /*!< Switch FLEXCOMM2 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM3);                 /*!< Switch FLEXCOMM3 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM4);                 /*!< Switch FLEXCOMM4 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM5);                 /*!< Switch FLEXCOMM5 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM6);                 /*!< Switch FLEXCOMM6 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM7);                 /*!< Switch FLEXCOMM7 to PLL0_DIV */
    CLOCK_AttachClk(kTRACE_DIV_to_TRACE);                 /*!< Switch TRACE to TRACE_DIV */

    /*!< Set SystemCoreClock variable. */
    SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
#endif
}

/*******************************************************************************
 ******************** Configuration BOARD_BootClockPLL150M *********************
 ******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockPLL150M
outputs:
- {id: ASYNCADC_clock.outFreq, value: 24 MHz}
- {id: FXCOM0_clock.outFreq, value: 48 MHz, locked: true, accuracy: '0.001'}
- {id: FXCOM1_clock.outFreq, value: 48 MHz}
- {id: FXCOM2_clock.outFreq, value: 48 MHz}
- {id: FXCOM3_clock.outFreq, value: 48 MHz}
- {id: FXCOM4_clock.outFreq, value: 48 MHz}
- {id: FXCOM5_clock.outFreq, value: 48 MHz}
- {id: FXCOM6_clock.outFreq, value: 48 MHz}
- {id: FXCOM7_clock.outFreq, value: 48 MHz}
- {id: OSC32KHZ_clock.outFreq, value: 32.768 kHz}
- {id: SCT_clock.outFreq, value: 150 MHz}
- {id: SYSTICK0_clock.outFreq, value: 150 MHz}
- {id: System_clock.outFreq, value: 150 MHz}
- {id: TRACE_clock.outFreq, value: 150 MHz}
- {id: USB1_PHY_clock.outFreq, value: 16 MHz}
- {id: UTICK_clock.outFreq, value: 1 MHz}
- {id: WDT_clock.outFreq, value: 1 MHz}
settings:
- {id: PLL0_Mode, value: Normal}
- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable}
- {id: ENABLE_CLKIN_ENA, value: Enabled}
- {id: ENABLE_PLL_USB_OUT, value: Enabled}
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
- {id: PMC_PDRUNCFG_PDEN_FRO32K_CFG, value: Power_up}
- {id: SYSCON.ADCCLKDIV.scale, value: '4', locked: true}
- {id: SYSCON.ADCCLKSEL.sel, value: ANACTRL.fro_hf_clk}
- {id: SYSCON.FCCLKSEL0.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FCCLKSEL1.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FCCLKSEL2.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FCCLKSEL3.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FCCLKSEL4.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FCCLKSEL5.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FCCLKSEL6.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FCCLKSEL7.sel, value: SYSCON.PLL0DIV}
- {id: SYSCON.FRGCTRL0_DIV.scale, value: '400'}
- {id: SYSCON.FRGCTRL1_DIV.scale, value: '400'}
- {id: SYSCON.FRGCTRL2_DIV.scale, value: '400'}
- {id: SYSCON.FRGCTRL3_DIV.scale, value: '400'}
- {id: SYSCON.FRGCTRL4_DIV.scale, value: '400'}
- {id: SYSCON.FRGCTRL5_DIV.scale, value: '400'}
- {id: SYSCON.FRGCTRL6_DIV.scale, value: '400'}
- {id: SYSCON.FRGCTRL7_DIV.scale, value: '400'}
- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
- {id: SYSCON.PLL0DIV.scale, value: '2'}
- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true}
- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true}
- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true}
- {id: SYSCON.SCTCLKSEL.sel, value: SYSCON.PLL0_BYPASS}
- {id: SYSCON.SYSTICKCLKSEL0.sel, value: SYSCON.SYSTICKCLKDIV0}
- {id: SYSCON.TRACECLKSEL.sel, value: SYSCON.TRACECLKDIV}
- {id: SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_CFG, value: Enabled}
- {id: UTICK_EN_CFG, value: Enable}
sources:
- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz}
- {id: RTC.fro_32k.outFreq, value: 32.768 kHz}
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
- {id: SYSCON.fro_1m.outFreq, value: 1 MHz}
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */

/*******************************************************************************
 * Variables for BOARD_BootClockPLL150M configuration
 ******************************************************************************/
/*******************************************************************************
 * Code for BOARD_BootClockPLL150M configuration
 ******************************************************************************/
void BOARD_BootClockPLL150M(void)
{
#ifndef SDK_SECONDARY_CORE
    /*!< Set up the clock sources */
    /*!< Configure FRO192M */
    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */

    /*!< Configure fro_1m */
    SYSCON->CLOCK_CTRL |=  SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK;                 /*!< Ensure fro_1m is on */

    CLOCK_SetupFROClocking(96000000U);                   /* Enable FRO HF(96MHz) output */

    /*!< Configure XTAL32M */
    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */
    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;       /* Enable clk_in to HS USB  */

    /*!< Configure RTC OSC */
    POWER_EnablePD(kPDRUNCFG_PD_XTAL32K);                /*!< Powered down the XTAL 32 kHz RTC oscillator */
    POWER_DisablePD(kPDRUNCFG_PD_FRO32K);                /*!< Powered the FRO 32 kHz RTC oscillator */
    CLOCK_AttachClk(kFRO32K_to_OSC32K);                  /*!< Switch OSC32K to FRO32K */
    CLOCK_EnableClock(kCLOCK_Rtc);                       /*!< Enable the RTC peripheral clock */
    RTC->CTRL &= ~RTC_CTRL_SWRESET_MASK;                 /*!< Make sure the reset bit is cleared */

    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK;               /* The FRO 1 MHz clock to UTICK is enabled. */

    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */

    /*!< Set up PLL */
    CLOCK_AttachClk(kEXT_CLK_to_PLL0);                    /*!< Switch PLL0CLKSEL to EXT_CLK */
    POWER_DisablePD(kPDRUNCFG_PD_PLL0);                  /* Ensure PLL is on  */
    POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
    const pll_setup_t pll0Setup = {
        .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
        .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
        .pllpdec = SYSCON_PLL0PDEC_PDIV(1U),
        .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
        .pllRate = 150000000U,
        .flags =  PLL_SETUPFLAG_WAITLOCK
    };
    CLOCK_SetPLL0Freq(&pll0Setup);                       /*!< Configure PLL0 to the desired values */

    /*!< Set up dividers */
    CLOCK_SetClkDiv(kCLOCK_DivArmTrClkDiv, 0U, true);               /*!< Reset TRACECLKDIV divider counter and halt it */
    CLOCK_SetClkDiv(kCLOCK_DivArmTrClkDiv, 1U, false);              /*!< Set TRACECLKDIV divider to value 1 */
    CLOCK_SetClkDiv(kCLOCK_DivSystickClk0, 0U, true);               /*!< Reset SYSTICKCLKDIV0 divider counter and halt it */
    CLOCK_SetClkDiv(kCLOCK_DivSystickClk0, 1U, false);              /*!< Set SYSTICKCLKDIV0 divider to value 1 */
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 144U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg0, 37120U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #endif
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg1, 144U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg1, 37120U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #endif
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg2, 144U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg2, 37120U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #endif
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg3, 144U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg3, 37120U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #endif
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg4, 144U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg4, 37120U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #endif
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg5, 144U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg5, 37120U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #endif
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg6, 144U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg6, 37120U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #endif
    #if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 3, 4)
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg7, 144U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #else
      CLOCK_SetClkDiv(kCLOCK_DivFlexFrg7, 37120U, false);         /*!< Set DIV to value 0xFF and MULT to value 144U in related FLEXFRGCTRL register */
    #endif
    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */
    CLOCK_SetClkDiv(kCLOCK_DivWdtClk, 0U, true);               /*!< Reset WDTCLKDIV divider counter and halt it */
    CLOCK_SetClkDiv(kCLOCK_DivWdtClk, 1U, false);         /*!< Set WDTCLKDIV divider to value 1 */
    CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, 0U, true);               /*!< Reset ADCCLKDIV divider counter and halt it */
    CLOCK_SetClkDiv(kCLOCK_DivAdcAsyncClk, 4U, false);         /*!< Set ADCCLKDIV divider to value 4 */
    CLOCK_SetClkDiv(kCLOCK_DivSctClk, 0U, true);               /*!< Reset SCTCLKDIV divider counter and halt it */
    CLOCK_SetClkDiv(kCLOCK_DivSctClk, 1U, false);         /*!< Set SCTCLKDIV divider to value 1 */
    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true);               /*!< Reset PLL0DIV divider counter and halt it */
    CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 2U, false);         /*!< Set PLL0DIV divider to value 2 */

    /*!< Set up clock selectors - Attach clocks to the peripheries */
    CLOCK_AttachClk(kPLL0_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL0 */
    CLOCK_AttachClk(kFRO_HF_to_ADC_CLK);                 /*!< Switch ADC_CLK to FRO_HF */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM0);                 /*!< Switch FLEXCOMM0 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM1);                 /*!< Switch FLEXCOMM1 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM2);                 /*!< Switch FLEXCOMM2 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM3);                 /*!< Switch FLEXCOMM3 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM4);                 /*!< Switch FLEXCOMM4 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM5);                 /*!< Switch FLEXCOMM5 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM6);                 /*!< Switch FLEXCOMM6 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM7);                 /*!< Switch FLEXCOMM7 to PLL0_DIV */
    CLOCK_AttachClk(kPLL0_to_SCT_CLK);                 /*!< Switch SCT_CLK to PLL0 */
    CLOCK_AttachClk(kTRACE_DIV_to_TRACE);                 /*!< Switch TRACE to TRACE_DIV */
    CLOCK_AttachClk(kSYSTICK_DIV0_to_SYSTICK0);                 /*!< Switch SYSTICK0 to SYSTICK_DIV0 */
    SYSCON->MAINCLKSELA = ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) | SYSCON_MAINCLKSELA_SEL(3U));    /*!< Switch MAINCLKSELA to FRO_HF even it is not used for MAINCLKSELB */

    /*!< Set SystemCoreClock variable. */
    SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
#endif
}

/*******************************************************************************
 ******************* Configuration BOARD_BootClockPLL1_150M ********************
 ******************************************************************************/
/* clang-format off */
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockPLL1_150M
outputs:
- {id: System_clock.outFreq, value: 150 MHz}
settings:
- {id: PLL1_Mode, value: Normal}
- {id: ENABLE_CLKIN_ENA, value: Enabled}
- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS}
- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN}
- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true}
- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true}
- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true}
sources:
- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/* clang-format on */

/*******************************************************************************
 * Variables for BOARD_BootClockPLL1_150M configuration
 ******************************************************************************/
/*******************************************************************************
 * Code for BOARD_BootClockPLL1_150M configuration
 ******************************************************************************/
void BOARD_BootClockPLL1_150M(void)
{
#ifndef SDK_SECONDARY_CORE
    /*!< Set up the clock sources */
    /*!< Configure FRO192M */
    POWER_DisablePD(kPDRUNCFG_PD_FRO192M);               /*!< Ensure FRO is on  */
    CLOCK_SetupFROClocking(12000000U);                   /*!< Set up FRO to the 12 MHz, just for sure */
    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);                /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */

    /*!< Configure XTAL32M */
    POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                        /* Ensure XTAL32M is powered */
    POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                       /* Ensure XTAL32M is powered */
    CLOCK_SetupExtClocking(16000000U);                            /* Enable clk_in clock */
    SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;       /* Enable clk_in from XTAL32M clock  */
    ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;    /* Enable clk_in to system  */

    POWER_SetVoltageForFreq(150000000U);                  /*!< Set voltage for the one of the fastest clock outputs: System clock output */
    CLOCK_SetFLASHAccessCyclesForFreq(150000000U);          /*!< Set FLASH wait states for core */

    /*!< Set up PLL1 */
    CLOCK_AttachClk(kEXT_CLK_to_PLL1);                    /*!< Switch PLL1CLKSEL to EXT_CLK */
    POWER_DisablePD(kPDRUNCFG_PD_PLL1);                  /* Ensure PLL is on  */
    const pll_setup_t pll1Setup = {
        .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U),
        .pllndec = SYSCON_PLL1NDEC_NDIV(8U),
        .pllpdec = SYSCON_PLL1PDEC_PDIV(1U),
        .pllmdec = SYSCON_PLL1MDEC_MDIV(150U),
        .pllRate = 150000000U,
        .flags =  PLL_SETUPFLAG_WAITLOCK
    };
    CLOCK_SetPLL1Freq(&pll1Setup);                        /*!< Configure PLL1 to the desired values */

    /*!< Set up dividers */
    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);         /*!< Set AHBCLKDIV divider to value 1 */

    /*!< Set up clock selectors - Attach clocks to the peripheries */
    CLOCK_AttachClk(kPLL1_to_MAIN_CLK);                 /*!< Switch MAIN_CLK to PLL1 */

    /*!< Set SystemCoreClock variable. */
    SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK;
#endif
}