1 | /* |
2 | * Copyright 2018, 2020 NXP |
3 | * All rights reserved. |
4 | * |
5 | * |
6 | * SPDX-License-Identifier: BSD-3-Clause |
7 | */ |
8 | |
9 | #include "fsl_lpuart.h" |
10 | |
11 | #include "fsl_adapter_uart.h" |
12 | |
13 | /*! @brief MACROs for whether a software idleline detection should be used. */ |
14 | #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) |
15 | #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) |
16 | #if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) |
17 | #define HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION (1) |
18 | #else /* HAL_UART_TRANSFER_MODE */ |
19 | #define HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION (0) |
20 | #endif /* HAL_UART_TRANSFER_MODE */ |
21 | #else /* UART_ADAPTER_NON_BLOCKING_MODE */ |
22 | #define HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION (1) |
23 | #endif /* UART_ADAPTER_NON_BLOCKING_MODE */ |
24 | #endif /* HAL_UART_DMA_ENABLE */ |
25 | |
26 | #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) |
27 | #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) |
28 | #include "fsl_component_timer_manager.h" |
29 | #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
30 | #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
31 | #include "fsl_lpuart_edma.h" |
32 | #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
33 | #include "fsl_lpuart_dma.h" |
34 | #endif |
35 | #if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT |
36 | #include "fsl_dmamux.h" |
37 | #endif |
38 | #ifdef DMA_IRQS |
39 | #define DMA_CHN_IRQS DMA_IRQS |
40 | #endif |
41 | #endif /* HAL_UART_DMA_ENABLE */ |
42 | |
43 | /******************************************************************************* |
44 | * Definitions |
45 | ******************************************************************************/ |
46 | #ifndef NDEBUG |
47 | #if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) |
48 | #undef assert |
49 | #define assert(n) |
50 | #endif |
51 | #endif |
52 | |
53 | #ifndef HAL_UART_ADAPTER_LOWPOWER_RESTORE |
54 | #define HAL_UART_ADAPTER_LOWPOWER_RESTORE (1) |
55 | #endif |
56 | |
57 | #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) |
58 | /*! @brief uart RX state structure. */ |
59 | typedef struct _hal_uart_dma_receive_state |
60 | { |
61 | uint8_t *volatile buffer; |
62 | volatile uint32_t bufferLength; |
63 | volatile uint32_t bufferSofar; |
64 | volatile uint32_t timeout; |
65 | volatile bool receiveAll; |
66 | } hal_uart_dma_receive_state_t; |
67 | |
68 | /*! @brief uart TX state structure. */ |
69 | typedef struct _hal_uart_dma_send_state |
70 | { |
71 | uint8_t *volatile buffer; |
72 | volatile uint32_t bufferLength; |
73 | volatile uint32_t bufferSofar; |
74 | volatile uint32_t timeout; |
75 | } hal_uart_dma_send_state_t; |
76 | |
77 | typedef struct _hal_uart_dma_state |
78 | { |
79 | struct _hal_uart_dma_state *next; |
80 | uint8_t instance; /* LPUART instance */ |
81 | hal_uart_dma_transfer_callback_t dma_callback; |
82 | void *dma_callback_param; |
83 | |
84 | #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
85 | lpuart_edma_handle_t edmaHandle; |
86 | edma_handle_t txEdmaHandle; |
87 | edma_handle_t rxEdmaHandle; |
88 | #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
89 | lpuart_dma_handle_t dmaHandle; |
90 | dma_handle_t txDmaHandle; |
91 | dma_handle_t rxDmaHandle; |
92 | #endif |
93 | hal_uart_dma_receive_state_t dma_rx; |
94 | hal_uart_dma_send_state_t dma_tx; |
95 | } hal_uart_dma_state_t; |
96 | |
97 | typedef struct _lpuart_dma_list |
98 | { |
99 | #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) |
100 | TIMER_MANAGER_HANDLE_DEFINE(timerManagerHandle); |
101 | #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
102 | hal_uart_dma_state_t *dma_list; |
103 | volatile int8_t activeCount; |
104 | } hal_lpuart_dma_list_t; |
105 | |
106 | static hal_lpuart_dma_list_t s_dmaHandleList; |
107 | #endif /* HAL_UART_DMA_ENABLE */ |
108 | |
109 | #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) |
110 | /*! @brief uart RX state structure. */ |
111 | typedef struct _hal_uart_receive_state |
112 | { |
113 | uint8_t *volatile buffer; |
114 | volatile uint32_t bufferLength; |
115 | volatile uint32_t bufferSofar; |
116 | } hal_uart_receive_state_t; |
117 | |
118 | /*! @brief uart TX state structure. */ |
119 | typedef struct _hal_uart_send_state |
120 | { |
121 | uint8_t *volatile buffer; |
122 | volatile uint32_t bufferLength; |
123 | volatile uint32_t bufferSofar; |
124 | } hal_uart_send_state_t; |
125 | #endif |
126 | /*! @brief uart state structure. */ |
127 | typedef struct _hal_uart_state |
128 | { |
129 | uint8_t instance; |
130 | #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) |
131 | hal_uart_block_mode_t mode; |
132 | hal_uart_transfer_callback_t callback; |
133 | void *callbackParam; |
134 | #if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) |
135 | lpuart_handle_t hardwareHandle; |
136 | #endif |
137 | hal_uart_receive_state_t rx; |
138 | hal_uart_send_state_t tx; |
139 | #endif |
140 | #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) |
141 | #if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U)) |
142 | uint32_t reg_BAUD; |
143 | uint32_t reg_CTRL; |
144 | uint32_t reg_WATER; |
145 | uint32_t reg_MODIR; |
146 | #else |
147 | hal_uart_config_t config; |
148 | #endif |
149 | #endif |
150 | #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) |
151 | hal_uart_dma_state_t *dmaHandle; |
152 | #endif /* HAL_UART_DMA_ENABLE */ |
153 | } hal_uart_state_t; |
154 | |
155 | /******************************************************************************* |
156 | * Prototypes |
157 | ******************************************************************************/ |
158 | |
159 | /******************************************************************************* |
160 | * Variables |
161 | ******************************************************************************/ |
162 | static LPUART_Type *const s_LpuartAdapterBase[] = LPUART_BASE_PTRS; |
163 | #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) |
164 | #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) |
165 | #if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U)) |
166 | static const clock_ip_name_t s_LpuartAdapterClock[] = LPUART_CLOCKS; |
167 | #endif /* HAL_UART_ADAPTER_LOWPOWER_RESTORE */ |
168 | #endif /* HAL_UART_ADAPTER_LOWPOWER */ |
169 | #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ |
170 | #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) |
171 | |
172 | #if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) |
173 | /* Array of LPUART IRQ number. */ |
174 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
175 | static const IRQn_Type s_LpuartRxIRQ[] = LPUART_RX_IRQS; |
176 | static const IRQn_Type s_LpuartTxIRQ[] = LPUART_TX_IRQS; |
177 | #else |
178 | static const IRQn_Type s_LpuartIRQ[] = LPUART_RX_TX_IRQS; |
179 | #endif |
180 | #endif |
181 | |
182 | #if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) |
183 | static hal_uart_state_t *s_UartState[sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)]; |
184 | #endif |
185 | |
186 | #endif |
187 | |
188 | #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) |
189 | #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) |
190 | #else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
191 | static hal_uart_dma_state_t *s_UartDmaState[sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *)]; |
192 | #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
193 | #endif /* HAL_UART_DMA_ENABLE */ |
194 | |
195 | /******************************************************************************* |
196 | * Code |
197 | ******************************************************************************/ |
198 | |
199 | #if ((defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) || \ |
200 | (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U))) |
201 | static hal_uart_status_t HAL_UartGetStatus(status_t status) |
202 | { |
203 | hal_uart_status_t uartStatus = kStatus_HAL_UartError; |
204 | switch (status) |
205 | { |
206 | case (int32_t)kStatus_Success: |
207 | uartStatus = kStatus_HAL_UartSuccess; |
208 | break; |
209 | case (int32_t)kStatus_LPUART_TxBusy: |
210 | uartStatus = kStatus_HAL_UartTxBusy; |
211 | break; |
212 | case (int32_t)kStatus_LPUART_RxBusy: |
213 | uartStatus = kStatus_HAL_UartRxBusy; |
214 | break; |
215 | case (int32_t)kStatus_LPUART_TxIdle: |
216 | uartStatus = kStatus_HAL_UartTxIdle; |
217 | break; |
218 | case (int32_t)kStatus_LPUART_RxIdle: |
219 | uartStatus = kStatus_HAL_UartRxIdle; |
220 | break; |
221 | case (int32_t)kStatus_LPUART_BaudrateNotSupport: |
222 | uartStatus = kStatus_HAL_UartBaudrateNotSupport; |
223 | break; |
224 | case (int32_t)kStatus_LPUART_NoiseError: |
225 | case (int32_t)kStatus_LPUART_FramingError: |
226 | case (int32_t)kStatus_LPUART_ParityError: |
227 | uartStatus = kStatus_HAL_UartProtocolError; |
228 | break; |
229 | default: |
230 | /*MISRA rule 16.4*/ |
231 | break; |
232 | } |
233 | return uartStatus; |
234 | } |
235 | #else |
236 | static hal_uart_status_t HAL_UartGetStatus(status_t status) |
237 | { |
238 | hal_uart_status_t uartStatus; |
239 | if ((int32_t)kStatus_Success == status) |
240 | { |
241 | uartStatus = kStatus_HAL_UartSuccess; /* Successfully */ |
242 | } |
243 | else |
244 | { |
245 | uartStatus = kStatus_HAL_UartError; /* Error occurs on HAL uart */ |
246 | } |
247 | return uartStatus; |
248 | } |
249 | #endif |
250 | |
251 | #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) |
252 | |
253 | #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) |
254 | #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) |
255 | #else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
256 | static void HAL_UartDMAIdlelineInterruptHandle(uint8_t instance) |
257 | { |
258 | hal_uart_dma_state_t *uartDmaHandle = s_UartDmaState[instance]; |
259 | hal_dma_callback_msg_t msg; |
260 | |
261 | assert(uartDmaHandle); |
262 | |
263 | if ((NULL != uartDmaHandle->dma_callback) && (NULL != uartDmaHandle->dma_rx.buffer)) |
264 | { |
265 | /* HAL_UartDMAGetReceiveCount(uartDmaHandle, &msg.dataSize); */ |
266 | /* HAL_UartDMAAbortReceive(uartDmaHandle); */ |
267 | |
268 | #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
269 | (void)LPUART_TransferGetReceiveCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], |
270 | &uartDmaHandle->edmaHandle, &msg.dataSize); |
271 | (void)LPUART_TransferAbortReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle); |
272 | #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
273 | |
274 | #endif /* FSL_FEATURE_SOC_EDMA_COUNT */ |
275 | msg.status = kStatus_HAL_UartDmaIdleline; |
276 | msg.data = uartDmaHandle->dma_rx.buffer; |
277 | uartDmaHandle->dma_rx.buffer = NULL; |
278 | |
279 | uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param); |
280 | } |
281 | } |
282 | #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
283 | #endif /* HAL_UART_DMA_ENABLE */ |
284 | |
285 | #if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) |
286 | static void HAL_UartCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *callbackParam) |
287 | { |
288 | hal_uart_state_t *uartHandle; |
289 | hal_uart_status_t uartStatus = HAL_UartGetStatus(status); |
290 | assert(callbackParam); |
291 | |
292 | uartHandle = (hal_uart_state_t *)callbackParam; |
293 | |
294 | assert(uartHandle->mode != kHAL_UartBlockMode); |
295 | |
296 | if (kStatus_HAL_UartProtocolError == uartStatus) |
297 | { |
298 | if (0U != uartHandle->hardwareHandle.rxDataSize) |
299 | { |
300 | uartStatus = kStatus_HAL_UartError; |
301 | } |
302 | } |
303 | |
304 | if (NULL != uartHandle->callback) |
305 | { |
306 | uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam); |
307 | } |
308 | } |
309 | |
310 | #else /* HAL_UART_TRANSFER_MODE */ |
311 | |
312 | static void HAL_UartInterruptHandle(uint8_t instance) |
313 | { |
314 | #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) |
315 | #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) |
316 | #else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
317 | hal_dma_callback_msg_t msg; |
318 | hal_uart_dma_state_t *uartDmaHandle = s_UartDmaState[instance]; |
319 | #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
320 | #endif /* HAL_UART_DMA_ENABLE */ |
321 | hal_uart_state_t *uartHandle = s_UartState[instance]; |
322 | uint32_t status; |
323 | #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
324 | uint8_t count; |
325 | #endif |
326 | |
327 | assert(NULL != uartHandle); |
328 | |
329 | status = LPUART_GetStatusFlags(s_LpuartAdapterBase[instance]); |
330 | |
331 | #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) |
332 | #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) |
333 | #else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
334 | /* DMA send complete interrupt. */ |
335 | if (instance == uartDmaHandle->instance) |
336 | { |
337 | if (NULL != uartDmaHandle->dma_tx.buffer) |
338 | { |
339 | if ((0U != ((uint32_t)kLPUART_TransmissionCompleteFlag & status)) && |
340 | (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & |
341 | (uint32_t)kLPUART_TransmissionCompleteFlag))) |
342 | { |
343 | /* Disable tx complete interrupt */ |
344 | (void)LPUART_DisableInterrupts(s_LpuartAdapterBase[instance], |
345 | (uint32_t)kLPUART_TransmissionCompleteFlag); |
346 | uartDmaHandle->edmaHandle.txState = 0; |
347 | msg.status = kStatus_HAL_UartDmaTxIdle; |
348 | msg.data = uartDmaHandle->dma_tx.buffer; |
349 | msg.dataSize = uartDmaHandle->dma_tx.bufferLength; |
350 | uartDmaHandle->dma_tx.buffer = NULL; |
351 | uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param); |
352 | } |
353 | } |
354 | /* DMA receive Idleline interrupt. */ |
355 | if ((NULL != uartDmaHandle->dma_rx.buffer) && (false == uartDmaHandle->dma_rx.receiveAll)) |
356 | { |
357 | if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && |
358 | (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & |
359 | (uint32_t)kLPUART_IdleLineInterruptEnable))) |
360 | { |
361 | HAL_UartDMAIdlelineInterruptHandle(instance); |
362 | (void)LPUART_ClearStatusFlags(s_LpuartAdapterBase[instance], (uint32_t)kLPUART_IdleLineFlag); |
363 | } |
364 | } |
365 | } |
366 | |
367 | #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
368 | #endif /* HAL_UART_DMA_ENABLE */ |
369 | |
370 | #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
371 | /* If RX overrun. */ |
372 | if ((uint32_t)kLPUART_RxOverrunFlag == ((uint32_t)kLPUART_RxOverrunFlag & status)) |
373 | { |
374 | /* Clear overrun flag, otherwise the RX does not work. */ |
375 | s_LpuartAdapterBase[instance]->STAT = |
376 | ((s_LpuartAdapterBase[instance]->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK); |
377 | } |
378 | #endif |
379 | |
380 | /* Receive data register full */ |
381 | if (((0U != ((uint32_t)kLPUART_RxDataRegFullFlag & status)) && |
382 | (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & |
383 | (uint32_t)kLPUART_RxDataRegFullInterruptEnable))) |
384 | #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
385 | || ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && |
386 | (0U != |
387 | (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & (uint32_t)kLPUART_IdleLineInterruptEnable))) |
388 | #endif |
389 | ) |
390 | { |
391 | if (NULL != uartHandle->rx.buffer) |
392 | { |
393 | #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
394 | /* Get the size that can be stored into buffer for this interrupt. */ |
395 | #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO |
396 | count = ((uint8_t)((s_LpuartAdapterBase[instance]->WATER & LPUART_WATER_RXCOUNT_MASK) >> |
397 | LPUART_WATER_RXCOUNT_SHIFT)); |
398 | #else |
399 | count = 1u; |
400 | #endif |
401 | while (0u != count) |
402 | { |
403 | count--; |
404 | #endif |
405 | uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = LPUART_ReadByte(s_LpuartAdapterBase[instance]); |
406 | if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength) |
407 | { |
408 | LPUART_DisableInterrupts( |
409 | s_LpuartAdapterBase[instance], (uint32_t)kLPUART_RxDataRegFullInterruptEnable | |
410 | (uint32_t)kLPUART_RxOverrunInterruptEnable |
411 | #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
412 | | (uint32_t)kLPUART_IdleLineInterruptEnable |
413 | #endif |
414 | ); |
415 | uartHandle->rx.buffer = NULL; |
416 | #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
417 | count = 0u; |
418 | #endif |
419 | if (NULL != uartHandle->callback) |
420 | { |
421 | uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam); |
422 | } |
423 | } |
424 | #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
425 | } |
426 | #endif |
427 | } |
428 | #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
429 | if ((0U != ((uint32_t)kLPUART_IdleLineFlag & status)) && |
430 | (0U != |
431 | (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & (uint32_t)kLPUART_IdleLineInterruptEnable))) |
432 | { |
433 | s_LpuartAdapterBase[instance]->STAT |= ((uint32_t)kLPUART_IdleLineFlag); |
434 | } |
435 | #endif |
436 | } |
437 | |
438 | /* Send data register empty and the interrupt is enabled. */ |
439 | if ((0U != (LPUART_STAT_TDRE_MASK & status)) && (0U != (LPUART_GetEnabledInterrupts(s_LpuartAdapterBase[instance]) & |
440 | (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable))) |
441 | { |
442 | if (NULL != uartHandle->tx.buffer) |
443 | { |
444 | #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
445 | /* Get the size that transmit buffer for this interrupt. */ |
446 | #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO |
447 | count = (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(s_LpuartAdapterBase[instance]) - |
448 | (uint8_t)((s_LpuartAdapterBase[instance]->WATER & LPUART_WATER_TXCOUNT_MASK) >> |
449 | LPUART_WATER_TXCOUNT_SHIFT); |
450 | #else |
451 | count = 1u; |
452 | #endif |
453 | while (0u != count) |
454 | { |
455 | count--; |
456 | #endif |
457 | LPUART_WriteByte(s_LpuartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]); |
458 | if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength) |
459 | { |
460 | LPUART_DisableInterrupts(s_LpuartAdapterBase[instance], |
461 | (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable); |
462 | uartHandle->tx.buffer = NULL; |
463 | #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
464 | count = 0u; |
465 | #endif |
466 | if (NULL != uartHandle->callback) |
467 | { |
468 | uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam); |
469 | } |
470 | } |
471 | #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
472 | } |
473 | #endif |
474 | } |
475 | } |
476 | |
477 | #if !(defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
478 | (void)LPUART_ClearStatusFlags(s_LpuartAdapterBase[instance], status); |
479 | #endif |
480 | } |
481 | #endif /* HAL_UART_TRANSFER_MODE */ |
482 | |
483 | #endif /* UART_ADAPTER_NON_BLOCKING_MODE */ |
484 | |
485 | static hal_uart_status_t HAL_UartInitCommon(hal_uart_handle_t handle, const hal_uart_config_t *config) |
486 | { |
487 | lpuart_config_t lpuartConfig; |
488 | status_t status; |
489 | hal_uart_status_t uartStatus = kStatus_HAL_UartSuccess; |
490 | |
491 | LPUART_GetDefaultConfig(&lpuartConfig); |
492 | lpuartConfig.baudRate_Bps = config->baudRate_Bps; |
493 | lpuartConfig.parityMode = (lpuart_parity_mode_t)config->parityMode; |
494 | lpuartConfig.stopBitCount = (lpuart_stop_bit_count_t)config->stopBitCount; |
495 | lpuartConfig.enableRx = (bool)config->enableRx; |
496 | lpuartConfig.enableTx = (bool)config->enableTx; |
497 | #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
498 | #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO |
499 | if (config->txFifoWatermark > 0U) |
500 | { |
501 | lpuartConfig.txFifoWatermark = |
502 | MIN(config->txFifoWatermark, |
503 | (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(s_LpuartAdapterBase[config->instance])) - |
504 | 1U; |
505 | } |
506 | if (config->rxFifoWatermark > 0U) |
507 | { |
508 | lpuartConfig.rxFifoWatermark = |
509 | MIN(config->rxFifoWatermark, |
510 | (uint8_t)FSL_FEATURE_LPUART_FIFO_SIZEn(s_LpuartAdapterBase[config->instance])) - |
511 | 1U; |
512 | } |
513 | #endif |
514 | #endif |
515 | #if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT |
516 | lpuartConfig.enableRxRTS = (bool)config->enableRxRTS; |
517 | lpuartConfig.enableTxCTS = (bool)config->enableTxCTS; |
518 | #endif /* FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT */ |
519 | |
520 | /* Idleline config */ |
521 | #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) |
522 | #else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
523 | lpuartConfig.rxIdleType = kLPUART_IdleTypeStopBit; |
524 | lpuartConfig.rxIdleConfig = kLPUART_IdleCharacter2; |
525 | #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
526 | |
527 | status = LPUART_Init(s_LpuartAdapterBase[config->instance], (void *)&lpuartConfig, config->srcClock_Hz); |
528 | |
529 | if ((int32_t)kStatus_Success != status) |
530 | { |
531 | uartStatus = HAL_UartGetStatus(status); /*Get current uart status*/ |
532 | } |
533 | |
534 | return uartStatus; |
535 | } |
536 | |
537 | hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *config) |
538 | { |
539 | hal_uart_state_t *uartHandle; |
540 | hal_uart_status_t uartStatus; |
541 | assert(NULL != handle); |
542 | assert(NULL != config); |
543 | assert(config->instance < (sizeof(s_LpuartAdapterBase) / sizeof(LPUART_Type *))); |
544 | assert(NULL != s_LpuartAdapterBase[config->instance]); |
545 | assert(HAL_UART_HANDLE_SIZE >= sizeof(hal_uart_state_t)); |
546 | |
547 | uartStatus = HAL_UartInitCommon(handle, config); |
548 | |
549 | if (kStatus_HAL_UartSuccess == uartStatus) |
550 | { |
551 | uartHandle = (hal_uart_state_t *)handle; |
552 | uartHandle->instance = config->instance; |
553 | #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) |
554 | uartHandle->dmaHandle = NULL; |
555 | #endif /* HAL_UART_DMA_ENABLE */ |
556 | |
557 | #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) |
558 | uartHandle->mode = config->mode; |
559 | #if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) |
560 | LPUART_TransferCreateHandle(s_LpuartAdapterBase[config->instance], &uartHandle->hardwareHandle, |
561 | (lpuart_transfer_callback_t)HAL_UartCallback, handle); |
562 | #else |
563 | s_UartState[uartHandle->instance] = uartHandle; |
564 | /* Enable interrupt in NVIC. */ |
565 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
566 | NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); |
567 | (void)EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); |
568 | NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); |
569 | (void)EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]); |
570 | #else |
571 | NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); |
572 | (void)EnableIRQ(s_LpuartIRQ[uartHandle->instance]); |
573 | #endif |
574 | #endif |
575 | |
576 | #endif |
577 | #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) |
578 | #if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U)) |
579 | uartHandle->reg_BAUD = s_LpuartAdapterBase[uartHandle->instance]->BAUD; |
580 | uartHandle->reg_CTRL = s_LpuartAdapterBase[uartHandle->instance]->CTRL; |
581 | uartHandle->reg_WATER = s_LpuartAdapterBase[uartHandle->instance]->WATER; |
582 | uartHandle->reg_MODIR = s_LpuartAdapterBase[uartHandle->instance]->MODIR; |
583 | #else |
584 | memcpy(&uartHandle->config, config, sizeof(hal_uart_config_t)); |
585 | #endif |
586 | #endif |
587 | } |
588 | |
589 | return uartStatus; |
590 | } |
591 | |
592 | hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle) |
593 | { |
594 | hal_uart_state_t *uartHandle; |
595 | |
596 | assert(NULL != handle); |
597 | |
598 | uartHandle = (hal_uart_state_t *)handle; |
599 | |
600 | LPUART_Deinit(s_LpuartAdapterBase[uartHandle->instance]); /*LPUART Deinitialization*/ |
601 | |
602 | #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) |
603 | |
604 | #if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) |
605 | s_UartState[uartHandle->instance] = NULL; |
606 | #endif |
607 | |
608 | #endif |
609 | |
610 | return kStatus_HAL_UartSuccess; |
611 | } |
612 | |
613 | hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) |
614 | { |
615 | hal_uart_state_t *uartHandle; |
616 | status_t status; |
617 | assert(NULL != handle); |
618 | assert(NULL != data); |
619 | assert(length > 0U); |
620 | |
621 | uartHandle = (hal_uart_state_t *)handle; |
622 | |
623 | status = LPUART_ReadBlocking(s_LpuartAdapterBase[uartHandle->instance], data, length); |
624 | |
625 | return HAL_UartGetStatus(status); |
626 | } |
627 | |
628 | hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length) |
629 | { |
630 | hal_uart_state_t *uartHandle; |
631 | |
632 | assert(NULL != handle); |
633 | assert(NULL != data); |
634 | assert(length > 0U); |
635 | |
636 | uartHandle = (hal_uart_state_t *)handle; |
637 | |
638 | (void)LPUART_WriteBlocking(s_LpuartAdapterBase[uartHandle->instance], data, length); |
639 | |
640 | return kStatus_HAL_UartSuccess; |
641 | } |
642 | |
643 | hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle) |
644 | { |
645 | assert(NULL != handle); |
646 | |
647 | return kStatus_HAL_UartSuccess; |
648 | } |
649 | |
650 | hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle) |
651 | { |
652 | #if (defined(HAL_UART_ADAPTER_LOWPOWER) && (HAL_UART_ADAPTER_LOWPOWER > 0U)) |
653 | hal_uart_state_t *uartHandle; |
654 | assert(handle); |
655 | |
656 | uartHandle = (hal_uart_state_t *)handle; |
657 | #if (defined(HAL_UART_ADAPTER_LOWPOWER_RESTORE) && (HAL_UART_ADAPTER_LOWPOWER_RESTORE > 0U)) |
658 | #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) |
659 | /* Enable lpuart clock */ |
660 | CLOCK_EnableClock(s_LpuartAdapterClock[uartHandle->instance]); |
661 | #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ |
662 | s_LpuartAdapterBase[uartHandle->instance]->BAUD = uartHandle->reg_BAUD; |
663 | s_LpuartAdapterBase[uartHandle->instance]->WATER = uartHandle->reg_WATER; |
664 | s_LpuartAdapterBase[uartHandle->instance]->MODIR = uartHandle->reg_MODIR; |
665 | #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO |
666 | /* Enable tx/rx FIFO */ |
667 | s_LpuartAdapterBase[uartHandle->instance]->FIFO |= (LPUART_FIFO_TXFE_MASK | LPUART_FIFO_RXFE_MASK); |
668 | /* Flush FIFO */ |
669 | s_LpuartAdapterBase[uartHandle->instance]->FIFO |= (LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK); |
670 | #endif /* FSL_FEATURE_LPUART_HAS_FIFO */ |
671 | s_LpuartAdapterBase[uartHandle->instance]->CTRL = uartHandle->reg_CTRL; |
672 | #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) |
673 | /* Enable interrupt in NVIC. */ |
674 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
675 | NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); |
676 | (void)EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); |
677 | NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); |
678 | (void)EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]); |
679 | #else |
680 | NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); |
681 | (void)EnableIRQ(s_LpuartIRQ[uartHandle->instance]); |
682 | #endif |
683 | if (uartHandle->mode == kHAL_UartNonBlockMode) |
684 | { |
685 | s_LpuartAdapterBase[uartHandle->instance]->CTRL |= LPUART_CTRL_RIE_MASK; |
686 | HAL_UartIsrFunction(uartHandle); |
687 | } |
688 | |
689 | #endif |
690 | #else |
691 | HAL_UartInit(handle, &uartHandle->config); |
692 | #endif |
693 | #endif |
694 | return kStatus_HAL_UartSuccess; |
695 | } |
696 | |
697 | #if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U)) |
698 | |
699 | #if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) |
700 | |
701 | hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle, |
702 | hal_uart_transfer_callback_t callback, |
703 | void *callbackParam) |
704 | { |
705 | hal_uart_state_t *uartHandle; |
706 | |
707 | assert(handle); |
708 | assert(0U != HAL_UART_TRANSFER_MODE); |
709 | |
710 | uartHandle = (hal_uart_state_t *)handle; |
711 | |
712 | assert(uartHandle->mode != kHAL_UartBlockMode); |
713 | |
714 | uartHandle->callbackParam = callbackParam; |
715 | uartHandle->callback = callback; |
716 | |
717 | return kStatus_HAL_UartSuccess; |
718 | } |
719 | |
720 | hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) |
721 | { |
722 | hal_uart_state_t *uartHandle; |
723 | status_t status; |
724 | assert(handle); |
725 | assert(transfer); |
726 | assert(0U != HAL_UART_TRANSFER_MODE); |
727 | |
728 | uartHandle = (hal_uart_state_t *)handle; |
729 | assert(uartHandle->mode != kHAL_UartBlockMode); |
730 | status = LPUART_TransferReceiveNonBlocking(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, |
731 | (lpuart_transfer_t *)(void *)transfer, NULL); |
732 | |
733 | return HAL_UartGetStatus(status); |
734 | } |
735 | |
736 | hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer) |
737 | { |
738 | hal_uart_state_t *uartHandle; |
739 | status_t status; |
740 | assert(handle); |
741 | assert(transfer); |
742 | assert(0U != HAL_UART_TRANSFER_MODE); |
743 | |
744 | uartHandle = (hal_uart_state_t *)handle; |
745 | assert(uartHandle->mode != kHAL_UartBlockMode); |
746 | status = LPUART_TransferSendNonBlocking(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, |
747 | (lpuart_transfer_t *)(void *)transfer); |
748 | |
749 | return HAL_UartGetStatus(status); |
750 | } |
751 | |
752 | hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count) |
753 | { |
754 | hal_uart_state_t *uartHandle; |
755 | status_t status; |
756 | assert(handle); |
757 | assert(count); |
758 | assert(0U != HAL_UART_TRANSFER_MODE); |
759 | |
760 | uartHandle = (hal_uart_state_t *)handle; |
761 | assert(uartHandle->mode != kHAL_UartBlockMode); |
762 | status = |
763 | LPUART_TransferGetReceiveCount(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); |
764 | |
765 | return HAL_UartGetStatus(status); |
766 | } |
767 | |
768 | hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count) |
769 | { |
770 | hal_uart_state_t *uartHandle; |
771 | status_t status; |
772 | assert(handle); |
773 | assert(count); |
774 | assert(0U != HAL_UART_TRANSFER_MODE); |
775 | |
776 | uartHandle = (hal_uart_state_t *)handle; |
777 | assert(uartHandle->mode != kHAL_UartBlockMode); |
778 | status = LPUART_TransferGetSendCount(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count); |
779 | |
780 | return HAL_UartGetStatus(status); |
781 | } |
782 | |
783 | hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle) |
784 | { |
785 | hal_uart_state_t *uartHandle; |
786 | assert(handle); |
787 | assert(0U != HAL_UART_TRANSFER_MODE); |
788 | |
789 | uartHandle = (hal_uart_state_t *)handle; |
790 | assert(uartHandle->mode != kHAL_UartBlockMode); |
791 | LPUART_TransferAbortReceive(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); |
792 | |
793 | return kStatus_HAL_UartSuccess; |
794 | } |
795 | |
796 | hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle) |
797 | { |
798 | hal_uart_state_t *uartHandle; |
799 | assert(handle); |
800 | assert(0U != HAL_UART_TRANSFER_MODE); |
801 | |
802 | uartHandle = (hal_uart_state_t *)handle; |
803 | assert(uartHandle->mode != kHAL_UartBlockMode); |
804 | LPUART_TransferAbortSend(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); |
805 | |
806 | return kStatus_HAL_UartSuccess; |
807 | } |
808 | |
809 | #else /* HAL_UART_TRANSFER_MODE */ |
810 | |
811 | /* None transactional API with non-blocking mode. */ |
812 | hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle, |
813 | hal_uart_transfer_callback_t callback, |
814 | void *callbackParam) |
815 | { |
816 | hal_uart_state_t *uartHandle; |
817 | |
818 | assert(NULL != handle); |
819 | assert(0U == HAL_UART_TRANSFER_MODE); |
820 | |
821 | uartHandle = (hal_uart_state_t *)handle; |
822 | assert(uartHandle->mode != kHAL_UartBlockMode); |
823 | uartHandle->callbackParam = callbackParam; |
824 | uartHandle->callback = callback; |
825 | |
826 | return kStatus_HAL_UartSuccess; |
827 | } |
828 | |
829 | hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) |
830 | { |
831 | hal_uart_state_t *uartHandle; |
832 | assert(NULL != handle); |
833 | assert(NULL != data); |
834 | assert(length > 0U); |
835 | assert(0U == HAL_UART_TRANSFER_MODE); |
836 | |
837 | uartHandle = (hal_uart_state_t *)handle; |
838 | assert(uartHandle->mode != kHAL_UartBlockMode); |
839 | if (NULL != uartHandle->rx.buffer) |
840 | { |
841 | return kStatus_HAL_UartRxBusy; |
842 | } |
843 | |
844 | uartHandle->rx.bufferLength = length; |
845 | uartHandle->rx.bufferSofar = 0; |
846 | uartHandle->rx.buffer = data; |
847 | LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_RxDataRegFullInterruptEnable | |
848 | (uint32_t)kLPUART_RxOverrunInterruptEnable |
849 | #if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) |
850 | | (uint32_t)kLPUART_IdleLineInterruptEnable |
851 | #endif |
852 | ); |
853 | return kStatus_HAL_UartSuccess; |
854 | } |
855 | |
856 | hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length) |
857 | { |
858 | hal_uart_state_t *uartHandle; |
859 | assert(NULL != handle); |
860 | assert(NULL != data); |
861 | assert(length > 0U); |
862 | assert(0U == HAL_UART_TRANSFER_MODE); |
863 | |
864 | uartHandle = (hal_uart_state_t *)handle; |
865 | assert(uartHandle->mode != kHAL_UartBlockMode); |
866 | if (NULL != uartHandle->tx.buffer) |
867 | { |
868 | return kStatus_HAL_UartTxBusy; |
869 | } |
870 | uartHandle->tx.bufferLength = length; |
871 | uartHandle->tx.bufferSofar = 0; |
872 | uartHandle->tx.buffer = data; |
873 | LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable); |
874 | return kStatus_HAL_UartSuccess; |
875 | } |
876 | |
877 | hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount) |
878 | { |
879 | hal_uart_state_t *uartHandle; |
880 | assert(NULL != handle); |
881 | assert(NULL != reCount); |
882 | assert(0U == HAL_UART_TRANSFER_MODE); |
883 | |
884 | uartHandle = (hal_uart_state_t *)handle; |
885 | assert(uartHandle->mode != kHAL_UartBlockMode); |
886 | if (NULL != uartHandle->rx.buffer) |
887 | { |
888 | *reCount = uartHandle->rx.bufferSofar; |
889 | return kStatus_HAL_UartSuccess; |
890 | } |
891 | return kStatus_HAL_UartError; |
892 | } |
893 | |
894 | hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount) |
895 | { |
896 | hal_uart_state_t *uartHandle; |
897 | assert(NULL != handle); |
898 | assert(NULL != seCount); |
899 | assert(0U == HAL_UART_TRANSFER_MODE); |
900 | |
901 | uartHandle = (hal_uart_state_t *)handle; |
902 | assert(uartHandle->mode != kHAL_UartBlockMode); |
903 | if (NULL != uartHandle->tx.buffer) |
904 | { |
905 | *seCount = uartHandle->tx.bufferSofar; |
906 | return kStatus_HAL_UartSuccess; |
907 | } |
908 | return kStatus_HAL_UartError; |
909 | } |
910 | |
911 | hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle) |
912 | { |
913 | hal_uart_state_t *uartHandle; |
914 | assert(NULL != handle); |
915 | assert(0U == HAL_UART_TRANSFER_MODE); |
916 | |
917 | uartHandle = (hal_uart_state_t *)handle; |
918 | assert(uartHandle->mode != kHAL_UartBlockMode); |
919 | if (NULL != uartHandle->rx.buffer) |
920 | { |
921 | LPUART_DisableInterrupts( |
922 | s_LpuartAdapterBase[uartHandle->instance], |
923 | (uint32_t)kLPUART_RxDataRegFullInterruptEnable | (uint32_t)kLPUART_RxOverrunInterruptEnable); |
924 | uartHandle->rx.buffer = NULL; |
925 | } |
926 | |
927 | return kStatus_HAL_UartSuccess; |
928 | } |
929 | |
930 | hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle) |
931 | { |
932 | hal_uart_state_t *uartHandle; |
933 | assert(NULL != handle); |
934 | assert(0U == HAL_UART_TRANSFER_MODE); |
935 | |
936 | uartHandle = (hal_uart_state_t *)handle; |
937 | assert(uartHandle->mode != kHAL_UartBlockMode); |
938 | if (NULL != uartHandle->tx.buffer) |
939 | { |
940 | LPUART_DisableInterrupts(s_LpuartAdapterBase[uartHandle->instance], |
941 | (uint32_t)kLPUART_TxDataRegEmptyInterruptEnable); |
942 | uartHandle->tx.buffer = NULL; |
943 | } |
944 | |
945 | return kStatus_HAL_UartSuccess; |
946 | } |
947 | |
948 | #endif /* HAL_UART_TRANSFER_MODE */ |
949 | |
950 | #if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U)) |
951 | |
952 | void HAL_UartIsrFunction(hal_uart_handle_t handle) |
953 | { |
954 | hal_uart_state_t *uartHandle; |
955 | assert(NULL != handle); |
956 | assert(0U != HAL_UART_TRANSFER_MODE); |
957 | |
958 | uartHandle = (hal_uart_state_t *)handle; |
959 | |
960 | #if 0 |
961 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
962 | DisableIRQ(s_LpuartRxIRQ[uartHandle->instance]); |
963 | DisableIRQ(s_LpuartTxIRQ[uartHandle->instance]); |
964 | #else |
965 | DisableIRQ(s_LpuartIRQ[uartHandle->instance]); |
966 | #endif |
967 | #endif |
968 | LPUART_TransferHandleIRQ(s_LpuartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle); |
969 | #if 0 |
970 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
971 | NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); |
972 | (void)EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); |
973 | NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); |
974 | (void)EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]); |
975 | #else |
976 | NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); |
977 | (void)EnableIRQ(s_LpuartIRQ[uartHandle->instance]); |
978 | #endif |
979 | #endif |
980 | } |
981 | |
982 | #else /* HAL_UART_TRANSFER_MODE */ |
983 | |
984 | void HAL_UartIsrFunction(hal_uart_handle_t handle) |
985 | { |
986 | hal_uart_state_t *uartHandle; |
987 | assert(NULL != handle); |
988 | assert(0U == HAL_UART_TRANSFER_MODE); |
989 | |
990 | uartHandle = (hal_uart_state_t *)handle; |
991 | |
992 | #if 0 |
993 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
994 | DisableIRQ(s_LpuartRxIRQ[uartHandle->instance]); |
995 | DisableIRQ(s_LpuartTxIRQ[uartHandle->instance]); |
996 | #else |
997 | DisableIRQ(s_LpuartIRQ[uartHandle->instance]); |
998 | #endif |
999 | #endif |
1000 | HAL_UartInterruptHandle(uartHandle->instance); |
1001 | #if 0 |
1002 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
1003 | NVIC_SetPriority((IRQn_Type)s_LpuartRxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); |
1004 | (void)EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); |
1005 | NVIC_SetPriority((IRQn_Type)s_LpuartTxIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); |
1006 | (void)EnableIRQ(s_LpuartTxIRQ[uartHandle->instance]); |
1007 | #else |
1008 | NVIC_SetPriority((IRQn_Type)s_LpuartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY); |
1009 | (void)EnableIRQ(s_LpuartIRQ[uartHandle->instance]); |
1010 | #endif |
1011 | #endif |
1012 | } |
1013 | |
1014 | #if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 |
1015 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
1016 | void LPUART0_LPUART1_RX_IRQHandler(void) |
1017 | { |
1018 | if ((s_UartState[0])) |
1019 | { |
1020 | if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || |
1021 | ((LPUART_STAT_RDRF_MASK & LPUART0->STAT) && (LPUART_CTRL_RIE_MASK & LPUART0->CTRL)) || |
1022 | ((LPUART_STAT_IDLE_MASK & LPUART0->STAT) && (LPUART_STAT_IDLE_MASK & LPUART0->CTRL))) |
1023 | { |
1024 | HAL_UartInterruptHandle(0); |
1025 | } |
1026 | } |
1027 | if ((s_UartState[1])) |
1028 | { |
1029 | if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || |
1030 | ((LPUART_STAT_RDRF_MASK & LPUART1->STAT) && (LPUART_CTRL_RIE_MASK & LPUART1->CTRL)) || |
1031 | ((LPUART_STAT_IDLE_MASK & LPUART1->STAT) && (LPUART_STAT_IDLE_MASK & LPUART1->CTRL))) |
1032 | { |
1033 | HAL_UartInterruptHandle(1); |
1034 | } |
1035 | } |
1036 | SDK_ISR_EXIT_BARRIER; |
1037 | } |
1038 | void LPUART0_LPUART1_TX_IRQHandler(void) |
1039 | { |
1040 | if ((s_UartState[0])) |
1041 | { |
1042 | if ((LPUART_STAT_OR_MASK & LPUART0->STAT) || |
1043 | ((LPUART0->STAT & LPUART_STAT_TDRE_MASK) && (LPUART0->CTRL & LPUART_CTRL_TIE_MASK)) || |
1044 | ((LPUART_CTRL_TCIE_MASK & LPUART0->STAT) && (LPUART_CTRL_TCIE_MASK & LPUART0->CTRL))) |
1045 | { |
1046 | HAL_UartInterruptHandle(0); |
1047 | } |
1048 | } |
1049 | if ((s_UartState[1])) |
1050 | { |
1051 | if ((LPUART_STAT_OR_MASK & LPUART1->STAT) || |
1052 | ((LPUART1->STAT & LPUART_STAT_TDRE_MASK) && (LPUART1->CTRL & LPUART_CTRL_TIE_MASK)) || |
1053 | ((LPUART_CTRL_TCIE_MASK & LPUART1->STAT) && (LPUART_CTRL_TCIE_MASK & LPUART1->CTRL))) |
1054 | { |
1055 | HAL_UartInterruptHandle(1); |
1056 | } |
1057 | } |
1058 | SDK_ISR_EXIT_BARRIER; |
1059 | } |
1060 | #else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ |
1061 | void LPUART0_LPUART1_IRQHandler(void); |
1062 | void LPUART0_LPUART1_IRQHandler(void) |
1063 | { |
1064 | uint32_t orMask; |
1065 | uint32_t rdrfMask; |
1066 | uint32_t rieMask; |
1067 | uint32_t tdreMask; |
1068 | uint32_t tieMask; |
1069 | uint32_t ilieMask; |
1070 | uint32_t tcieMask; |
1071 | if (NULL != (s_UartState[0])) |
1072 | { |
1073 | orMask = LPUART_STAT_OR_MASK & LPUART0->STAT; |
1074 | rdrfMask = LPUART_STAT_RDRF_MASK & LPUART0->STAT; |
1075 | rieMask = LPUART_CTRL_RIE_MASK & LPUART0->CTRL; |
1076 | tdreMask = LPUART0->STAT & LPUART_STAT_TDRE_MASK; |
1077 | tieMask = LPUART0->CTRL & LPUART_CTRL_TIE_MASK; |
1078 | ilieMask = LPUART0->STAT & LPUART_CTRL_ILIE_MASK; |
1079 | tcieMask = LPUART0->STAT & LPUART_CTRL_TCIE_MASK; |
1080 | if ((bool)orMask || ((bool)rdrfMask && (bool)rieMask) || ((bool)tdreMask && (bool)tieMask) || (bool)ilieMask || |
1081 | (bool)tcieMask) |
1082 | { |
1083 | HAL_UartInterruptHandle(0); |
1084 | } |
1085 | } |
1086 | if (NULL != (s_UartState[1])) |
1087 | { |
1088 | orMask = LPUART_STAT_OR_MASK & LPUART1->STAT; |
1089 | rdrfMask = LPUART_STAT_RDRF_MASK & LPUART1->STAT; |
1090 | rieMask = LPUART_CTRL_RIE_MASK & LPUART1->CTRL; |
1091 | tdreMask = LPUART1->STAT & LPUART_STAT_TDRE_MASK; |
1092 | tieMask = LPUART1->CTRL & LPUART_CTRL_TIE_MASK; |
1093 | ilieMask = LPUART1->STAT & LPUART_CTRL_ILIE_MASK; |
1094 | tcieMask = LPUART1->STAT & LPUART_CTRL_TCIE_MASK; |
1095 | if ((bool)orMask || ((bool)rdrfMask && (bool)rieMask) || ((bool)tdreMask && (bool)tieMask) || (bool)ilieMask || |
1096 | (bool)tcieMask) |
1097 | { |
1098 | HAL_UartInterruptHandle(1); |
1099 | } |
1100 | } |
1101 | SDK_ISR_EXIT_BARRIER; |
1102 | } |
1103 | #endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ |
1104 | #endif /* FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 */ |
1105 | |
1106 | #if defined(LPUART0) |
1107 | #if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) |
1108 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
1109 | void LPUART0_TX_IRQHandler(void) |
1110 | { |
1111 | HAL_UartInterruptHandle(0); |
1112 | SDK_ISR_EXIT_BARRIER; |
1113 | } |
1114 | void LPUART0_RX_IRQHandler(void) |
1115 | { |
1116 | HAL_UartInterruptHandle(0); |
1117 | SDK_ISR_EXIT_BARRIER; |
1118 | } |
1119 | #else |
1120 | void LPUART0_IRQHandler(void); |
1121 | void LPUART0_IRQHandler(void) |
1122 | { |
1123 | HAL_UartInterruptHandle(0); |
1124 | SDK_ISR_EXIT_BARRIER; |
1125 | } |
1126 | #endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ |
1127 | #endif /* FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 */ |
1128 | #endif /* LPUART0 */ |
1129 | |
1130 | #if defined(LPUART1) |
1131 | #if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) |
1132 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
1133 | void LPUART1_TX_IRQHandler(void) |
1134 | { |
1135 | HAL_UartInterruptHandle(1); |
1136 | SDK_ISR_EXIT_BARRIER; |
1137 | } |
1138 | void LPUART1_RX_IRQHandler(void) |
1139 | { |
1140 | HAL_UartInterruptHandle(1); |
1141 | SDK_ISR_EXIT_BARRIER; |
1142 | } |
1143 | #else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ |
1144 | void LPUART1_IRQHandler(void); |
1145 | void LPUART1_IRQHandler(void) |
1146 | { |
1147 | HAL_UartInterruptHandle(1); |
1148 | SDK_ISR_EXIT_BARRIER; |
1149 | } |
1150 | #endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ |
1151 | #endif /* FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 */ |
1152 | #endif /* LPUART1 */ |
1153 | |
1154 | #if defined(LPUART2) |
1155 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
1156 | void LPUART2_TX_IRQHandler(void) |
1157 | { |
1158 | HAL_UartInterruptHandle(2); |
1159 | SDK_ISR_EXIT_BARRIER; |
1160 | } |
1161 | void LPUART2_RX_IRQHandler(void) |
1162 | { |
1163 | HAL_UartInterruptHandle(2); |
1164 | SDK_ISR_EXIT_BARRIER; |
1165 | } |
1166 | #else |
1167 | void LPUART2_IRQHandler(void); |
1168 | void LPUART2_IRQHandler(void) |
1169 | { |
1170 | HAL_UartInterruptHandle(2); |
1171 | SDK_ISR_EXIT_BARRIER; |
1172 | } |
1173 | #endif |
1174 | #endif /* LPUART2 */ |
1175 | |
1176 | #if defined(LPUART3) |
1177 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
1178 | void LPUART3_TX_IRQHandler(void) |
1179 | { |
1180 | HAL_UartInterruptHandle(3); |
1181 | SDK_ISR_EXIT_BARRIER; |
1182 | } |
1183 | void LPUART3_RX_IRQHandler(void) |
1184 | { |
1185 | HAL_UartInterruptHandle(3); |
1186 | SDK_ISR_EXIT_BARRIER; |
1187 | } |
1188 | #else |
1189 | void LPUART3_IRQHandler(void); |
1190 | void LPUART3_IRQHandler(void) |
1191 | { |
1192 | HAL_UartInterruptHandle(3); |
1193 | SDK_ISR_EXIT_BARRIER; |
1194 | } |
1195 | #endif |
1196 | #endif /* LPUART3 */ |
1197 | |
1198 | #if defined(LPUART4) |
1199 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
1200 | void LPUART4_TX_IRQHandler(void) |
1201 | { |
1202 | HAL_UartInterruptHandle(4); |
1203 | SDK_ISR_EXIT_BARRIER; |
1204 | } |
1205 | void LPUART4_RX_IRQHandler(void) |
1206 | { |
1207 | HAL_UartInterruptHandle(4); |
1208 | SDK_ISR_EXIT_BARRIER; |
1209 | } |
1210 | #else |
1211 | void LPUART4_IRQHandler(void); |
1212 | void LPUART4_IRQHandler(void) |
1213 | { |
1214 | HAL_UartInterruptHandle(4); |
1215 | SDK_ISR_EXIT_BARRIER; |
1216 | } |
1217 | #endif |
1218 | #endif /* LPUART4 */ |
1219 | |
1220 | #if defined(LPUART5) |
1221 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
1222 | void LPUART5_TX_IRQHandler(void) |
1223 | { |
1224 | HAL_UartInterruptHandle(5); |
1225 | SDK_ISR_EXIT_BARRIER; |
1226 | } |
1227 | void LPUART5_RX_IRQHandler(void) |
1228 | { |
1229 | HAL_UartInterruptHandle(5); |
1230 | SDK_ISR_EXIT_BARRIER; |
1231 | } |
1232 | #else |
1233 | void LPUART5_IRQHandler(void); |
1234 | void LPUART5_IRQHandler(void) |
1235 | { |
1236 | HAL_UartInterruptHandle(5); |
1237 | SDK_ISR_EXIT_BARRIER; |
1238 | } |
1239 | #endif |
1240 | #endif /* LPUART5 */ |
1241 | |
1242 | #if defined(LPUART6) |
1243 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
1244 | void LPUART6_TX_IRQHandler(void) |
1245 | { |
1246 | HAL_UartInterruptHandle(6); |
1247 | SDK_ISR_EXIT_BARRIER; |
1248 | } |
1249 | void LPUART6_RX_IRQHandler(void) |
1250 | { |
1251 | HAL_UartInterruptHandle(6); |
1252 | SDK_ISR_EXIT_BARRIER; |
1253 | } |
1254 | #else |
1255 | void LPUART6_IRQHandler(void); |
1256 | void LPUART6_IRQHandler(void) |
1257 | { |
1258 | HAL_UartInterruptHandle(6); |
1259 | SDK_ISR_EXIT_BARRIER; |
1260 | } |
1261 | #endif |
1262 | #endif /* LPUART6 */ |
1263 | |
1264 | #if defined(LPUART7) |
1265 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
1266 | void LPUART7_TX_IRQHandler(void) |
1267 | { |
1268 | HAL_UartInterruptHandle(7); |
1269 | SDK_ISR_EXIT_BARRIER; |
1270 | } |
1271 | void LPUART7_RX_IRQHandler(void) |
1272 | { |
1273 | HAL_UartInterruptHandle(7); |
1274 | SDK_ISR_EXIT_BARRIER; |
1275 | } |
1276 | #else |
1277 | void LPUART7_IRQHandler(void); |
1278 | void LPUART7_IRQHandler(void) |
1279 | { |
1280 | HAL_UartInterruptHandle(7); |
1281 | SDK_ISR_EXIT_BARRIER; |
1282 | } |
1283 | #endif |
1284 | #endif /* LPUART7 */ |
1285 | |
1286 | #if defined(LPUART8) |
1287 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
1288 | void LPUART8_TX_IRQHandler(void) |
1289 | { |
1290 | HAL_UartInterruptHandle(8); |
1291 | SDK_ISR_EXIT_BARRIER; |
1292 | } |
1293 | void LPUART8_RX_IRQHandler(void) |
1294 | { |
1295 | HAL_UartInterruptHandle(8); |
1296 | SDK_ISR_EXIT_BARRIER; |
1297 | } |
1298 | #else |
1299 | void LPUART8_IRQHandler(void); |
1300 | void LPUART8_IRQHandler(void) |
1301 | { |
1302 | HAL_UartInterruptHandle(8); |
1303 | SDK_ISR_EXIT_BARRIER; |
1304 | } |
1305 | #endif |
1306 | #endif /* LPUART8 */ |
1307 | |
1308 | #if defined(CM4_0__LPUART) |
1309 | void M4_0_LPUART_IRQHandler(void); |
1310 | void M4_0_LPUART_IRQHandler(void) |
1311 | { |
1312 | HAL_UartInterruptHandle(LPUART_GetInstance(CM4_0__LPUART)); |
1313 | SDK_ISR_EXIT_BARRIER; |
1314 | } |
1315 | #endif |
1316 | |
1317 | #if defined(CM4_1__LPUART) |
1318 | void M4_1_LPUART_IRQHandler(void); |
1319 | void M4_1_LPUART_IRQHandler(void) |
1320 | { |
1321 | HAL_UartInterruptHandle(LPUART_GetInstance(CM4_1__LPUART)); |
1322 | SDK_ISR_EXIT_BARRIER; |
1323 | } |
1324 | #endif |
1325 | |
1326 | #if defined(CM4__LPUART) |
1327 | void M4_LPUART_IRQHandler(void); |
1328 | void M4_LPUART_IRQHandler(void) |
1329 | { |
1330 | HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(CM4__LPUART)); |
1331 | SDK_ISR_EXIT_BARRIER; |
1332 | } |
1333 | #endif |
1334 | |
1335 | #if defined(DMA__LPUART0) |
1336 | void DMA_UART0_INT_IRQHandler(void) |
1337 | { |
1338 | HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART0)); |
1339 | SDK_ISR_EXIT_BARRIER; |
1340 | } |
1341 | #endif |
1342 | |
1343 | #if defined(DMA__LPUART1) |
1344 | void DMA_UART1_INT_IRQHandler(void) |
1345 | { |
1346 | HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART1)); |
1347 | SDK_ISR_EXIT_BARRIER; |
1348 | } |
1349 | #endif |
1350 | |
1351 | #if defined(DMA__LPUART2) |
1352 | void DMA_UART2_INT_IRQHandler(void) |
1353 | { |
1354 | HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART2)); |
1355 | SDK_ISR_EXIT_BARRIER; |
1356 | } |
1357 | #endif |
1358 | |
1359 | #if defined(DMA__LPUART3) |
1360 | void DMA_UART3_INT_IRQHandler(void) |
1361 | { |
1362 | HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART3)); |
1363 | SDK_ISR_EXIT_BARRIER; |
1364 | } |
1365 | #endif |
1366 | |
1367 | #if defined(DMA__LPUART4) |
1368 | void DMA_UART4_INT_IRQHandler(void) |
1369 | { |
1370 | HAL_UartInterruptHandle(LPUART_GetInstance(DMA__LPUART4)); |
1371 | SDK_ISR_EXIT_BARRIER; |
1372 | } |
1373 | #endif |
1374 | |
1375 | #if defined(ADMA__LPUART0) |
1376 | void ADMA_UART0_INT_IRQHandler(void); |
1377 | void ADMA_UART0_INT_IRQHandler(void) |
1378 | { |
1379 | HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART0)); |
1380 | SDK_ISR_EXIT_BARRIER; |
1381 | } |
1382 | #endif |
1383 | |
1384 | #if defined(ADMA__LPUART1) |
1385 | void ADMA_UART1_INT_IRQHandler(void); |
1386 | void ADMA_UART1_INT_IRQHandler(void) |
1387 | { |
1388 | HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART1)); |
1389 | SDK_ISR_EXIT_BARRIER; |
1390 | } |
1391 | #endif |
1392 | |
1393 | #if defined(ADMA__LPUART2) |
1394 | void ADMA_UART2_INT_IRQHandler(void); |
1395 | void ADMA_UART2_INT_IRQHandler(void) |
1396 | { |
1397 | HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART2)); |
1398 | SDK_ISR_EXIT_BARRIER; |
1399 | } |
1400 | #endif |
1401 | |
1402 | #if defined(ADMA__LPUART3) |
1403 | void ADMA_UART3_INT_IRQHandler(void); |
1404 | void ADMA_UART3_INT_IRQHandler(void) |
1405 | { |
1406 | HAL_UartInterruptHandle((uint8_t)LPUART_GetInstance(ADMA__LPUART3)); |
1407 | SDK_ISR_EXIT_BARRIER; |
1408 | } |
1409 | #endif |
1410 | |
1411 | #endif /* HAL_UART_TRANSFER_MODE */ |
1412 | |
1413 | #endif /* UART_ADAPTER_NON_BLOCKING_MODE */ |
1414 | |
1415 | #if (defined(HAL_UART_DMA_ENABLE) && (HAL_UART_DMA_ENABLE > 0U)) |
1416 | static void LPUART_DMACallbacks(LPUART_Type *base, lpuart_edma_handle_t *handle, status_t status, void *userData) |
1417 | { |
1418 | hal_uart_dma_state_t *uartDmaHandle; |
1419 | hal_uart_status_t uartStatus = HAL_UartGetStatus(status); |
1420 | hal_dma_callback_msg_t msg; |
1421 | assert(handle); |
1422 | |
1423 | (void)memset(&msg, 0, sizeof(hal_dma_callback_msg_t)); |
1424 | uartDmaHandle = (hal_uart_dma_state_t *)userData; |
1425 | |
1426 | if (NULL != uartDmaHandle->dma_callback) |
1427 | { |
1428 | if (kStatus_HAL_UartTxIdle == uartStatus) |
1429 | { |
1430 | msg.status = kStatus_HAL_UartDmaTxIdle; |
1431 | msg.data = uartDmaHandle->dma_tx.buffer; |
1432 | msg.dataSize = uartDmaHandle->dma_tx.bufferLength; |
1433 | uartDmaHandle->dma_tx.buffer = NULL; |
1434 | } |
1435 | else if (kStatus_HAL_UartRxIdle == uartStatus) |
1436 | { |
1437 | msg.status = kStatus_HAL_UartDmaRxIdle; |
1438 | msg.data = uartDmaHandle->dma_rx.buffer; |
1439 | msg.dataSize = uartDmaHandle->dma_rx.bufferLength; |
1440 | uartDmaHandle->dma_rx.buffer = NULL; |
1441 | } |
1442 | else |
1443 | { |
1444 | /* Misra Rule 15.7 fix */ |
1445 | } |
1446 | |
1447 | uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param); |
1448 | } |
1449 | } |
1450 | |
1451 | #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) |
1452 | static void TimeoutTimer_Callbcak(void *param) |
1453 | { |
1454 | hal_lpuart_dma_list_t *uartDmaHandleList; |
1455 | hal_uart_dma_state_t *uartDmaHandle; |
1456 | hal_dma_callback_msg_t msg; |
1457 | uint32_t newReceived = 0U; |
1458 | |
1459 | (void)memset(&msg, 0, sizeof(hal_dma_callback_msg_t)); |
1460 | uartDmaHandleList = (hal_lpuart_dma_list_t *)param; |
1461 | uartDmaHandle = uartDmaHandleList->dma_list; |
1462 | |
1463 | while (NULL != uartDmaHandle) |
1464 | { |
1465 | if ((NULL != uartDmaHandle->dma_rx.buffer) && (false == uartDmaHandle->dma_rx.receiveAll)) |
1466 | { |
1467 | /* HAL_UartDMAGetReceiveCount(uartDmaHandle, &msg.dataSize); */ |
1468 | #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
1469 | |
1470 | #elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
1471 | LPUART_TransferGetReceiveCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle, |
1472 | &msg.dataSize); |
1473 | #endif /* FSL_FEATURE_SOC_EDMA_COUNT */ |
1474 | newReceived = msg.dataSize - uartDmaHandle->dma_rx.bufferSofar; |
1475 | uartDmaHandle->dma_rx.bufferSofar = msg.dataSize; |
1476 | |
1477 | /* 1, If it is in idle state. */ |
1478 | if ((0U == newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar)) |
1479 | { |
1480 | uartDmaHandle->dma_rx.timeout++; |
1481 | if (uartDmaHandle->dma_rx.timeout >= HAL_UART_DMA_IDLELINE_TIMEOUT) |
1482 | { |
1483 | /* HAL_UartDMAAbortReceive(uartDmaHandle); */ |
1484 | #if (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
1485 | |
1486 | #elif (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
1487 | LPUART_TransferAbortReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], |
1488 | &uartDmaHandle->edmaHandle); |
1489 | #endif /* FSL_FEATURE_SOC_EDMA_COUNT */ |
1490 | msg.data = uartDmaHandle->dma_rx.buffer; |
1491 | msg.status = kStatus_HAL_UartDmaIdleline; |
1492 | uartDmaHandle->dma_rx.buffer = NULL; |
1493 | uartDmaHandle->dma_callback(uartDmaHandle, &msg, uartDmaHandle->dma_callback_param); |
1494 | } |
1495 | } |
1496 | /* 2, If got new data again. */ |
1497 | if ((0U < newReceived) && (0U < uartDmaHandle->dma_rx.bufferSofar)) |
1498 | { |
1499 | uartDmaHandle->dma_rx.timeout = 0U; |
1500 | } |
1501 | } |
1502 | |
1503 | uartDmaHandle = uartDmaHandle->next; |
1504 | } |
1505 | } |
1506 | #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
1507 | |
1508 | hal_uart_dma_status_t HAL_UartDMAInit(hal_uart_handle_t handle, |
1509 | hal_uart_dma_handle_t dmaHandle, |
1510 | hal_uart_dma_config_t *dmaConfig) |
1511 | { |
1512 | hal_uart_state_t *uartHandle; |
1513 | hal_uart_dma_state_t *uartDmaHandle; |
1514 | #if (defined(HAL_UART_DMA_INIT_ENABLE) && (HAL_UART_DMA_INIT_ENABLE > 0U)) |
1515 | edma_config_t config; |
1516 | #endif |
1517 | assert(handle); |
1518 | |
1519 | uartHandle = (hal_uart_state_t *)handle; |
1520 | uartDmaHandle = (hal_uart_dma_state_t *)dmaHandle; |
1521 | uartHandle->dmaHandle = uartDmaHandle; |
1522 | |
1523 | /* DMA init process. */ |
1524 | uartDmaHandle->instance = dmaConfig->uart_instance; |
1525 | |
1526 | #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
1527 | #if (defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && (FSL_FEATURE_SOC_DMAMUX_COUNT > 0U)) |
1528 | dma_mux_configure_t *dmaMux = dmaConfig->dma_mux_configure; |
1529 | /* Set channel for LPUART */ |
1530 | DMAMUX_Type *dmaMuxBases[] = DMAMUX_BASE_PTRS; |
1531 | #if (defined(HAL_UART_DMA_INIT_ENABLE) && (HAL_UART_DMA_INIT_ENABLE > 0U)) |
1532 | DMAMUX_Init(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance]); |
1533 | #endif |
1534 | |
1535 | DMAMUX_SetSource(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->tx_channel, |
1536 | dmaMux->dma_dmamux_configure.tx_request); |
1537 | DMAMUX_SetSource(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->rx_channel, |
1538 | dmaMux->dma_dmamux_configure.rx_request); |
1539 | DMAMUX_EnableChannel(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->tx_channel); |
1540 | DMAMUX_EnableChannel(dmaMuxBases[dmaMux->dma_dmamux_configure.dma_mux_instance], dmaConfig->rx_channel); |
1541 | |
1542 | #endif /* FSL_FEATURE_SOC_DMAMUX_COUNT */ |
1543 | /* Init the EDMA module */ |
1544 | DMA_Type *dmaBases[] = DMA_BASE_PTRS; |
1545 | IRQn_Type s_edmaIRQNumbers[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS; |
1546 | #if (defined(HAL_UART_DMA_INIT_ENABLE) && (HAL_UART_DMA_INIT_ENABLE > 0U)) |
1547 | |
1548 | EDMA_GetDefaultConfig(&config); |
1549 | EDMA_Init(dmaBases[dmaConfig->dma_instance], &config); |
1550 | #endif |
1551 | EDMA_CreateHandle(&uartDmaHandle->txEdmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel); |
1552 | EDMA_CreateHandle(&uartDmaHandle->rxEdmaHandle, dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel); |
1553 | #if (defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && (FSL_FEATURE_EDMA_HAS_CHANNEL_MUX > 0U)) |
1554 | dma_channel_mux_configure_t *dmaChannelMux = dmaConfig->dma_channel_mux_configure; |
1555 | EDMA_SetChannelMux(dmaBases[dmaConfig->dma_instance], dmaConfig->tx_channel, |
1556 | dmaChannelMux->dma_dmamux_configure.dma_tx_channel_mux); |
1557 | EDMA_SetChannelMux(dmaBases[dmaConfig->dma_instance], dmaConfig->rx_channel, |
1558 | dmaChannelMux->dma_dmamux_configure.dma_rx_channel_mux); |
1559 | #endif /* FSL_FEATURE_EDMA_HAS_CHANNEL_MUX */ |
1560 | |
1561 | #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
1562 | #endif /* FSL_FEATURE_SOC_EDMA_COUNT */ |
1563 | NVIC_SetPriority(s_edmaIRQNumbers[dmaConfig->dma_instance][dmaConfig->tx_channel], (uint32_t)HAL_UART_ISR_PRIORITY); |
1564 | NVIC_SetPriority(s_edmaIRQNumbers[dmaConfig->dma_instance][dmaConfig->rx_channel], (uint32_t)HAL_UART_ISR_PRIORITY); |
1565 | #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) |
1566 | #else /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
1567 | s_UartDmaState[uartDmaHandle->instance] = uartDmaHandle; |
1568 | |
1569 | /* Enable RX interrupt for detecting the IDLE line interrupt. */ |
1570 | LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_IdleLineInterruptEnable); |
1571 | #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ |
1572 | (void)EnableIRQ(s_LpuartRxIRQ[uartHandle->instance]); |
1573 | #else /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ |
1574 | (void)EnableIRQ(s_LpuartIRQ[uartHandle->instance]); |
1575 | #endif /* FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ */ |
1576 | #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
1577 | |
1578 | if (0 == s_dmaHandleList.activeCount) |
1579 | { |
1580 | s_dmaHandleList.dma_list = uartDmaHandle; |
1581 | uartDmaHandle->next = NULL; |
1582 | s_dmaHandleList.activeCount++; |
1583 | |
1584 | #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) |
1585 | timer_status_t timerStatus; |
1586 | timerStatus = TM_Open((timer_handle_t)s_dmaHandleList.timerManagerHandle); |
1587 | assert(kStatus_TimerSuccess == timerStatus); |
1588 | |
1589 | timerStatus = TM_InstallCallback((timer_handle_t)s_dmaHandleList.timerManagerHandle, TimeoutTimer_Callbcak, |
1590 | &s_dmaHandleList); |
1591 | assert(kStatus_TimerSuccess == timerStatus); |
1592 | |
1593 | (void)TM_Start((timer_handle_t)s_dmaHandleList.timerManagerHandle, (uint8_t)kTimerModeIntervalTimer, 1); |
1594 | |
1595 | (void)timerStatus; |
1596 | #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
1597 | } |
1598 | else |
1599 | { |
1600 | uartDmaHandle->next = s_dmaHandleList.dma_list; |
1601 | s_dmaHandleList.dma_list = uartDmaHandle; |
1602 | } |
1603 | |
1604 | return kStatus_HAL_UartDmaSuccess; |
1605 | } |
1606 | |
1607 | hal_uart_dma_status_t HAL_UartDMADeinit(hal_uart_handle_t handle) |
1608 | { |
1609 | hal_uart_state_t *uartHandle; |
1610 | hal_uart_dma_state_t *uartDmaHandle; |
1611 | hal_uart_dma_state_t *prev; |
1612 | hal_uart_dma_state_t *curr; |
1613 | |
1614 | assert(handle); |
1615 | |
1616 | uartHandle = (hal_uart_state_t *)handle; |
1617 | uartDmaHandle = uartHandle->dmaHandle; |
1618 | |
1619 | uartHandle->dmaHandle = NULL; |
1620 | |
1621 | assert(uartDmaHandle); |
1622 | |
1623 | /* Abort rx/tx */ |
1624 | |
1625 | #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
1626 | /* Here we should not abort before create transfer handle. */ |
1627 | if (NULL != uartDmaHandle->edmaHandle.rxEdmaHandle) |
1628 | { |
1629 | LPUART_TransferAbortReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle); |
1630 | } |
1631 | if (NULL != uartDmaHandle->edmaHandle.txEdmaHandle) |
1632 | { |
1633 | LPUART_TransferAbortSendEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle); |
1634 | } |
1635 | #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
1636 | |
1637 | #endif /* FSL_FEATURE_SOC_EDMA_COUNT */ |
1638 | |
1639 | /* Disable rx/tx channels */ |
1640 | |
1641 | /* Remove handle from list */ |
1642 | prev = NULL; |
1643 | curr = s_dmaHandleList.dma_list; |
1644 | while (curr != NULL) |
1645 | { |
1646 | if (curr == uartDmaHandle) |
1647 | { |
1648 | /* 1, if it is the first one */ |
1649 | if (prev == NULL) |
1650 | { |
1651 | s_dmaHandleList.dma_list = curr->next; |
1652 | } |
1653 | /* 2, if it is the last one */ |
1654 | else if (curr->next == NULL) |
1655 | { |
1656 | prev->next = NULL; |
1657 | } |
1658 | /* 3, if it is in the middle */ |
1659 | else |
1660 | { |
1661 | prev->next = curr->next; |
1662 | } |
1663 | break; |
1664 | } |
1665 | |
1666 | prev = curr; |
1667 | curr = curr->next; |
1668 | } |
1669 | |
1670 | /* Reset all handle data. */ |
1671 | (void)memset(uartDmaHandle, 0, sizeof(hal_uart_dma_state_t)); |
1672 | |
1673 | s_dmaHandleList.activeCount = (s_dmaHandleList.activeCount > 0) ? (s_dmaHandleList.activeCount - 1) : 0; |
1674 | #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) |
1675 | if (0 == s_dmaHandleList.activeCount) |
1676 | { |
1677 | (void)TM_Close((timer_handle_t)s_dmaHandleList.timerManagerHandle); |
1678 | } |
1679 | #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
1680 | |
1681 | return kStatus_HAL_UartDmaSuccess; |
1682 | } |
1683 | |
1684 | hal_uart_dma_status_t HAL_UartDMATransferInstallCallback(hal_uart_handle_t handle, |
1685 | hal_uart_dma_transfer_callback_t callback, |
1686 | void *callbackParam) |
1687 | { |
1688 | hal_uart_state_t *uartHandle; |
1689 | hal_uart_dma_state_t *uartDmaHandle; |
1690 | |
1691 | assert(handle); |
1692 | |
1693 | uartHandle = (hal_uart_state_t *)handle; |
1694 | uartDmaHandle = uartHandle->dmaHandle; |
1695 | |
1696 | assert(uartDmaHandle); |
1697 | |
1698 | uartDmaHandle->dma_callback = callback; |
1699 | uartDmaHandle->dma_callback_param = callbackParam; |
1700 | |
1701 | #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
1702 | LPUART_TransferCreateHandleEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle, |
1703 | LPUART_DMACallbacks, uartDmaHandle, &uartDmaHandle->txEdmaHandle, |
1704 | &uartDmaHandle->rxEdmaHandle); |
1705 | #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
1706 | #endif /* FSL_FEATURE_SOC_EDMA_COUNT */ |
1707 | |
1708 | return kStatus_HAL_UartDmaSuccess; |
1709 | } |
1710 | |
1711 | hal_uart_dma_status_t HAL_UartDMATransferReceive(hal_uart_handle_t handle, |
1712 | uint8_t *data, |
1713 | size_t length, |
1714 | bool receiveAll) |
1715 | { |
1716 | hal_uart_state_t *uartHandle; |
1717 | hal_uart_dma_state_t *uartDmaHandle; |
1718 | lpuart_transfer_t xfer; |
1719 | |
1720 | assert(handle); |
1721 | assert(data); |
1722 | |
1723 | uartHandle = (hal_uart_state_t *)handle; |
1724 | uartDmaHandle = uartHandle->dmaHandle; |
1725 | |
1726 | assert(uartDmaHandle); |
1727 | |
1728 | if (NULL == uartDmaHandle->dma_rx.buffer) |
1729 | { |
1730 | uartDmaHandle->dma_rx.buffer = data; |
1731 | uartDmaHandle->dma_rx.bufferLength = length; |
1732 | uartDmaHandle->dma_rx.bufferSofar = 0U; |
1733 | uartDmaHandle->dma_rx.timeout = 0U; |
1734 | uartDmaHandle->dma_rx.receiveAll = receiveAll; |
1735 | } |
1736 | else |
1737 | { |
1738 | /* Already in reading process. */ |
1739 | return kStatus_HAL_UartDmaRxBusy; |
1740 | } |
1741 | |
1742 | xfer.data = data; |
1743 | xfer.dataSize = length; |
1744 | |
1745 | #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
1746 | (void)LPUART_ReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle, &xfer); |
1747 | #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
1748 | #endif /* FSL_FEATURE_SOC_EDMA_COUNT */ |
1749 | |
1750 | #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) |
1751 | #else |
1752 | /* Enable RX interrupt for detecting the IDLE line interrupt. */ |
1753 | LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_IdleLineInterruptEnable); |
1754 | #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
1755 | |
1756 | return kStatus_HAL_UartDmaSuccess; |
1757 | } |
1758 | |
1759 | hal_uart_dma_status_t HAL_UartDMATransferSend(hal_uart_handle_t handle, uint8_t *data, size_t length) |
1760 | { |
1761 | hal_uart_state_t *uartHandle; |
1762 | hal_uart_dma_state_t *uartDmaHandle; |
1763 | lpuart_transfer_t xfer; |
1764 | |
1765 | assert(handle); |
1766 | assert(data); |
1767 | |
1768 | uartHandle = (hal_uart_state_t *)handle; |
1769 | uartDmaHandle = uartHandle->dmaHandle; |
1770 | |
1771 | assert(uartDmaHandle); |
1772 | |
1773 | if (NULL == uartDmaHandle->dma_tx.buffer) |
1774 | { |
1775 | uartDmaHandle->dma_tx.buffer = data; |
1776 | uartDmaHandle->dma_tx.bufferLength = length; |
1777 | uartDmaHandle->dma_tx.bufferSofar = 0U; |
1778 | } |
1779 | else |
1780 | { |
1781 | /* Already in writing process. */ |
1782 | return kStatus_HAL_UartDmaTxBusy; |
1783 | } |
1784 | |
1785 | xfer.data = data; |
1786 | xfer.dataSize = length; |
1787 | |
1788 | #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
1789 | (void)LPUART_SendEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle, &xfer); |
1790 | #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
1791 | #endif /* FSL_FEATURE_SOC_EDMA_COUNT */ |
1792 | |
1793 | #if (defined(HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION) && (HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION > 0U)) |
1794 | #else |
1795 | /* Enable RX interrupt for detecting the IDLE line interrupt. */ |
1796 | LPUART_EnableInterrupts(s_LpuartAdapterBase[uartHandle->instance], (uint32_t)kLPUART_IdleLineInterruptEnable); |
1797 | #endif /* HAL_UART_DMA_USE_SOFTWARE_IDLELINE_DETECTION */ |
1798 | |
1799 | return kStatus_HAL_UartDmaSuccess; |
1800 | } |
1801 | |
1802 | hal_uart_dma_status_t HAL_UartDMAGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount) |
1803 | { |
1804 | hal_uart_state_t *uartHandle; |
1805 | hal_uart_dma_state_t *uartDmaHandle; |
1806 | |
1807 | assert(handle); |
1808 | |
1809 | uartHandle = (hal_uart_state_t *)handle; |
1810 | uartDmaHandle = uartHandle->dmaHandle; |
1811 | |
1812 | assert(uartDmaHandle); |
1813 | |
1814 | #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
1815 | if (kStatus_Success != LPUART_TransferGetReceiveCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], |
1816 | &uartDmaHandle->edmaHandle, reCount)) |
1817 | { |
1818 | return kStatus_HAL_UartDmaError; |
1819 | } |
1820 | |
1821 | #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
1822 | #endif /* FSL_FEATURE_SOC_EDMA_COUNT */ |
1823 | |
1824 | return kStatus_HAL_UartDmaSuccess; |
1825 | } |
1826 | |
1827 | hal_uart_dma_status_t HAL_UartDMAGetSendCount(hal_uart_handle_t handle, uint32_t *seCount) |
1828 | { |
1829 | hal_uart_state_t *uartHandle; |
1830 | hal_uart_dma_state_t *uartDmaHandle; |
1831 | |
1832 | assert(handle); |
1833 | |
1834 | uartHandle = (hal_uart_state_t *)handle; |
1835 | uartDmaHandle = uartHandle->dmaHandle; |
1836 | |
1837 | assert(uartDmaHandle); |
1838 | |
1839 | #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
1840 | if (kStatus_Success != LPUART_TransferGetSendCountEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], |
1841 | &uartDmaHandle->edmaHandle, seCount)) |
1842 | { |
1843 | return kStatus_HAL_UartDmaError; |
1844 | } |
1845 | #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
1846 | |
1847 | #endif /* FSL_FEATURE_SOC_EDMA_COUNT */ |
1848 | |
1849 | return kStatus_HAL_UartDmaSuccess; |
1850 | } |
1851 | |
1852 | hal_uart_dma_status_t HAL_UartDMAAbortReceive(hal_uart_handle_t handle) |
1853 | { |
1854 | hal_uart_state_t *uartHandle; |
1855 | hal_uart_dma_state_t *uartDmaHandle; |
1856 | |
1857 | assert(handle); |
1858 | |
1859 | uartHandle = (hal_uart_state_t *)handle; |
1860 | uartDmaHandle = uartHandle->dmaHandle; |
1861 | |
1862 | assert(uartDmaHandle); |
1863 | |
1864 | #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
1865 | LPUART_TransferAbortReceiveEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle); |
1866 | #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
1867 | #endif /* FSL_FEATURE_SOC_EDMA_COUNT */ |
1868 | |
1869 | return kStatus_HAL_UartDmaSuccess; |
1870 | } |
1871 | |
1872 | hal_uart_dma_status_t HAL_UartDMAAbortSend(hal_uart_handle_t handle) |
1873 | { |
1874 | hal_uart_state_t *uartHandle; |
1875 | hal_uart_dma_state_t *uartDmaHandle; |
1876 | |
1877 | assert(handle); |
1878 | |
1879 | uartHandle = (hal_uart_state_t *)handle; |
1880 | uartDmaHandle = uartHandle->dmaHandle; |
1881 | |
1882 | assert(uartDmaHandle); |
1883 | |
1884 | #if (defined(FSL_FEATURE_SOC_EDMA_COUNT) && (FSL_FEATURE_SOC_EDMA_COUNT > 0U)) |
1885 | LPUART_TransferAbortSendEDMA(s_LpuartAdapterBase[uartDmaHandle->instance], &uartDmaHandle->edmaHandle); |
1886 | #elif (defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT > 0U)) |
1887 | #endif /* FSL_FEATURE_SOC_EDMA_COUNT */ |
1888 | |
1889 | return kStatus_HAL_UartDmaSuccess; |
1890 | } |
1891 | #endif /* HAL_UART_DMA_ENABLE */ |
1892 | |