1 | /* |
2 | * How to setup clock using clock driver functions: |
3 | * |
4 | * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. |
5 | * |
6 | * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. |
7 | * |
8 | * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out. |
9 | * |
10 | * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out. |
11 | * |
12 | * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings. |
13 | * |
14 | */ |
15 | |
16 | /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* |
17 | !!GlobalInfo |
18 | product: Clocks v9.0 |
19 | processor: MIMXRT1062xxxxA |
20 | package_id: MIMXRT1062DVL6A |
21 | mcu_data: ksdk2_0 |
22 | processor_version: 11.0.1 |
23 | board: MIMXRT1060-EVK |
24 | * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ |
25 | |
26 | #include "clock_config.h" |
27 | #include "fsl_iomuxc.h" |
28 | |
29 | /******************************************************************************* |
30 | * Definitions |
31 | ******************************************************************************/ |
32 | |
33 | /******************************************************************************* |
34 | * Variables |
35 | ******************************************************************************/ |
36 | /* System clock frequency. */ |
37 | extern uint32_t SystemCoreClock; |
38 | |
39 | /******************************************************************************* |
40 | ************************ BOARD_InitBootClocks function ************************ |
41 | ******************************************************************************/ |
42 | void BOARD_InitBootClocks(void) |
43 | { |
44 | BOARD_BootClockRUN(); |
45 | } |
46 | |
47 | /******************************************************************************* |
48 | ********************** Configuration BOARD_BootClockRUN *********************** |
49 | ******************************************************************************/ |
50 | /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* |
51 | !!Configuration |
52 | name: BOARD_BootClockRUN |
53 | called_from_default_init: true |
54 | outputs: |
55 | - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz} |
56 | - {id: CAN_CLK_ROOT.outFreq, value: 30 MHz} |
57 | - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz} |
58 | - {id: CLK_1M.outFreq, value: 1 MHz} |
59 | - {id: CLK_24M.outFreq, value: 24 MHz} |
60 | - {id: CSI_CLK_ROOT.outFreq, value: 12 MHz} |
61 | - {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz} |
62 | - {id: ENET_125M_CLK.outFreq, value: 2.4 MHz} |
63 | - {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz} |
64 | - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz} |
65 | - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz} |
66 | - {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz} |
67 | - {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz} |
68 | - {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz} |
69 | - {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz} |
70 | - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz} |
71 | - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz} |
72 | - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz} |
73 | - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz} |
74 | - {id: LVDS1_CLK.outFreq, value: 1.2 GHz} |
75 | - {id: MQS_MCLK.outFreq, value: 1080/17 MHz} |
76 | - {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz} |
77 | - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz} |
78 | - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz} |
79 | - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz} |
80 | - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz} |
81 | - {id: SAI1_MCLK3.outFreq, value: 30 MHz} |
82 | - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz} |
83 | - {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz} |
84 | - {id: SAI2_MCLK3.outFreq, value: 30 MHz} |
85 | - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz} |
86 | - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz} |
87 | - {id: SAI3_MCLK3.outFreq, value: 30 MHz} |
88 | - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz} |
89 | - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz} |
90 | - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz} |
91 | - {id: UART_CLK_ROOT.outFreq, value: 80 MHz} |
92 | - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz} |
93 | - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz} |
94 | settings: |
95 | - {id: CCM.AHB_PODF.scale, value: '1', locked: true} |
96 | - {id: CCM.ARM_PODF.scale, value: '2', locked: true} |
97 | - {id: CCM.CAN_CLK_SEL.sel, value: CCM.PLL3_SW_60M_CLK_DIV} |
98 | - {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true} |
99 | - {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} |
100 | - {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true} |
101 | - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK} |
102 | - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true} |
103 | - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true} |
104 | - {id: CCM.SEMC_PODF.scale, value: '8'} |
105 | - {id: CCM.TRACE_PODF.scale, value: '3', locked: true} |
106 | - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1} |
107 | - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true} |
108 | - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true} |
109 | - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true} |
110 | - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true} |
111 | - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK} |
112 | - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0} |
113 | - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1} |
114 | - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2} |
115 | - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3} |
116 | - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3} |
117 | - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0} |
118 | - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true} |
119 | - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true} |
120 | - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1} |
121 | - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2} |
122 | - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3} |
123 | - {id: CCM_ANALOG.PLL4.denom, value: '50'} |
124 | - {id: CCM_ANALOG.PLL4.div, value: '47'} |
125 | - {id: CCM_ANALOG.PLL5.denom, value: '1'} |
126 | - {id: CCM_ANALOG.PLL5.div, value: '40'} |
127 | - {id: CCM_ANALOG.PLL5.num, value: '0'} |
128 | - {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'} |
129 | - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'} |
130 | sources: |
131 | - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true} |
132 | * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ |
133 | |
134 | /******************************************************************************* |
135 | * Variables for BOARD_BootClockRUN configuration |
136 | ******************************************************************************/ |
137 | const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = |
138 | { |
139 | .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */ |
140 | .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ |
141 | }; |
142 | const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = |
143 | { |
144 | .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */ |
145 | .numerator = 0, /* 30 bit numerator of fractional loop divider */ |
146 | .denominator = 1, /* 30 bit denominator of fractional loop divider */ |
147 | .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ |
148 | }; |
149 | const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = |
150 | { |
151 | .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */ |
152 | .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */ |
153 | }; |
154 | /******************************************************************************* |
155 | * Code for BOARD_BootClockRUN configuration |
156 | ******************************************************************************/ |
157 | void BOARD_BootClockRUN(void) |
158 | { |
159 | /* Init RTC OSC clock frequency. */ |
160 | CLOCK_SetRtcXtalFreq(32768U); |
161 | /* Enable 1MHz clock output. */ |
162 | XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK; |
163 | /* Use free 1MHz clock output. */ |
164 | XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK; |
165 | /* Set XTAL 24MHz clock frequency. */ |
166 | CLOCK_SetXtalFreq(24000000U); |
167 | /* Enable XTAL 24MHz clock source. */ |
168 | CLOCK_InitExternalClk(0); |
169 | /* Enable internal RC. */ |
170 | CLOCK_InitRcOsc24M(); |
171 | /* Switch clock source to external OSC. */ |
172 | CLOCK_SwitchOsc(kCLOCK_XtalOsc); |
173 | /* Set Oscillator ready counter value. */ |
174 | CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127); |
175 | /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */ |
176 | CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */ |
177 | CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ |
178 | /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */ |
179 | DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13); |
180 | /* Waiting for DCDC_STS_DC_OK bit is asserted */ |
181 | while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) |
182 | { |
183 | } |
184 | /* Set AHB_PODF. */ |
185 | CLOCK_SetDiv(kCLOCK_AhbDiv, 0); |
186 | /* Disable IPG clock gate. */ |
187 | CLOCK_DisableClock(kCLOCK_Adc1); |
188 | CLOCK_DisableClock(kCLOCK_Adc2); |
189 | CLOCK_DisableClock(kCLOCK_Xbar1); |
190 | CLOCK_DisableClock(kCLOCK_Xbar2); |
191 | CLOCK_DisableClock(kCLOCK_Xbar3); |
192 | /* Set IPG_PODF. */ |
193 | CLOCK_SetDiv(kCLOCK_IpgDiv, 3); |
194 | /* Set ARM_PODF. */ |
195 | CLOCK_SetDiv(kCLOCK_ArmDiv, 1); |
196 | /* Set PERIPH_CLK2_PODF. */ |
197 | CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0); |
198 | /* Disable PERCLK clock gate. */ |
199 | CLOCK_DisableClock(kCLOCK_Gpt1); |
200 | CLOCK_DisableClock(kCLOCK_Gpt1S); |
201 | CLOCK_DisableClock(kCLOCK_Gpt2); |
202 | CLOCK_DisableClock(kCLOCK_Gpt2S); |
203 | CLOCK_DisableClock(kCLOCK_Pit); |
204 | /* Set PERCLK_PODF. */ |
205 | CLOCK_SetDiv(kCLOCK_PerclkDiv, 1); |
206 | /* Disable USDHC1 clock gate. */ |
207 | CLOCK_DisableClock(kCLOCK_Usdhc1); |
208 | /* Set USDHC1_PODF. */ |
209 | CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1); |
210 | /* Set Usdhc1 clock source. */ |
211 | CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0); |
212 | /* Disable USDHC2 clock gate. */ |
213 | CLOCK_DisableClock(kCLOCK_Usdhc2); |
214 | /* Set USDHC2_PODF. */ |
215 | CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1); |
216 | /* Set Usdhc2 clock source. */ |
217 | CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0); |
218 | /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. |
219 | * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. |
220 | * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ |
221 | #ifndef SKIP_SYSCLK_INIT |
222 | /* Disable Semc clock gate. */ |
223 | CLOCK_DisableClock(kCLOCK_Semc); |
224 | /* Set SEMC_PODF. */ |
225 | CLOCK_SetDiv(kCLOCK_SemcDiv, 7); |
226 | /* Set Semc alt clock source. */ |
227 | CLOCK_SetMux(kCLOCK_SemcAltMux, 0); |
228 | /* Set Semc clock source. */ |
229 | CLOCK_SetMux(kCLOCK_SemcMux, 0); |
230 | #endif |
231 | /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. |
232 | * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. |
233 | * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ |
234 | #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) |
235 | /* Disable Flexspi clock gate. */ |
236 | CLOCK_DisableClock(kCLOCK_FlexSpi); |
237 | /* Set FLEXSPI_PODF. */ |
238 | CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1); |
239 | /* Set Flexspi clock source. */ |
240 | CLOCK_SetMux(kCLOCK_FlexspiMux, 3); |
241 | #endif |
242 | /* Disable Flexspi2 clock gate. */ |
243 | CLOCK_DisableClock(kCLOCK_FlexSpi2); |
244 | /* Set FLEXSPI2_PODF. */ |
245 | CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1); |
246 | /* Set Flexspi2 clock source. */ |
247 | CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1); |
248 | /* Disable CSI clock gate. */ |
249 | CLOCK_DisableClock(kCLOCK_Csi); |
250 | /* Set CSI_PODF. */ |
251 | CLOCK_SetDiv(kCLOCK_CsiDiv, 1); |
252 | /* Set Csi clock source. */ |
253 | CLOCK_SetMux(kCLOCK_CsiMux, 0); |
254 | /* Disable LPSPI clock gate. */ |
255 | CLOCK_DisableClock(kCLOCK_Lpspi1); |
256 | CLOCK_DisableClock(kCLOCK_Lpspi2); |
257 | CLOCK_DisableClock(kCLOCK_Lpspi3); |
258 | CLOCK_DisableClock(kCLOCK_Lpspi4); |
259 | /* Set LPSPI_PODF. */ |
260 | CLOCK_SetDiv(kCLOCK_LpspiDiv, 4); |
261 | /* Set Lpspi clock source. */ |
262 | CLOCK_SetMux(kCLOCK_LpspiMux, 2); |
263 | /* Disable TRACE clock gate. */ |
264 | CLOCK_DisableClock(kCLOCK_Trace); |
265 | /* Set TRACE_PODF. */ |
266 | CLOCK_SetDiv(kCLOCK_TraceDiv, 2); |
267 | /* Set Trace clock source. */ |
268 | CLOCK_SetMux(kCLOCK_TraceMux, 2); |
269 | /* Disable SAI1 clock gate. */ |
270 | CLOCK_DisableClock(kCLOCK_Sai1); |
271 | /* Set SAI1_CLK_PRED. */ |
272 | CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3); |
273 | /* Set SAI1_CLK_PODF. */ |
274 | CLOCK_SetDiv(kCLOCK_Sai1Div, 1); |
275 | /* Set Sai1 clock source. */ |
276 | CLOCK_SetMux(kCLOCK_Sai1Mux, 0); |
277 | /* Disable SAI2 clock gate. */ |
278 | CLOCK_DisableClock(kCLOCK_Sai2); |
279 | /* Set SAI2_CLK_PRED. */ |
280 | CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3); |
281 | /* Set SAI2_CLK_PODF. */ |
282 | CLOCK_SetDiv(kCLOCK_Sai2Div, 1); |
283 | /* Set Sai2 clock source. */ |
284 | CLOCK_SetMux(kCLOCK_Sai2Mux, 0); |
285 | /* Disable SAI3 clock gate. */ |
286 | CLOCK_DisableClock(kCLOCK_Sai3); |
287 | /* Set SAI3_CLK_PRED. */ |
288 | CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3); |
289 | /* Set SAI3_CLK_PODF. */ |
290 | CLOCK_SetDiv(kCLOCK_Sai3Div, 1); |
291 | /* Set Sai3 clock source. */ |
292 | CLOCK_SetMux(kCLOCK_Sai3Mux, 0); |
293 | /* Disable Lpi2c clock gate. */ |
294 | CLOCK_DisableClock(kCLOCK_Lpi2c1); |
295 | CLOCK_DisableClock(kCLOCK_Lpi2c2); |
296 | CLOCK_DisableClock(kCLOCK_Lpi2c3); |
297 | /* Set LPI2C_CLK_PODF. */ |
298 | CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0); |
299 | /* Set Lpi2c clock source. */ |
300 | CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); |
301 | /* Disable CAN clock gate. */ |
302 | CLOCK_DisableClock(kCLOCK_Can1); |
303 | CLOCK_DisableClock(kCLOCK_Can2); |
304 | CLOCK_DisableClock(kCLOCK_Can3); |
305 | CLOCK_DisableClock(kCLOCK_Can1S); |
306 | CLOCK_DisableClock(kCLOCK_Can2S); |
307 | CLOCK_DisableClock(kCLOCK_Can3S); |
308 | /* Set CAN_CLK_PODF. */ |
309 | CLOCK_SetDiv(kCLOCK_CanDiv, 1); |
310 | /* Set Can clock source. */ |
311 | CLOCK_SetMux(kCLOCK_CanMux, 0); |
312 | /* Disable UART clock gate. */ |
313 | CLOCK_DisableClock(kCLOCK_Lpuart1); |
314 | CLOCK_DisableClock(kCLOCK_Lpuart2); |
315 | CLOCK_DisableClock(kCLOCK_Lpuart3); |
316 | CLOCK_DisableClock(kCLOCK_Lpuart4); |
317 | CLOCK_DisableClock(kCLOCK_Lpuart5); |
318 | CLOCK_DisableClock(kCLOCK_Lpuart6); |
319 | CLOCK_DisableClock(kCLOCK_Lpuart7); |
320 | CLOCK_DisableClock(kCLOCK_Lpuart8); |
321 | /* Set UART_CLK_PODF. */ |
322 | CLOCK_SetDiv(kCLOCK_UartDiv, 0); |
323 | /* Set Uart clock source. */ |
324 | CLOCK_SetMux(kCLOCK_UartMux, 0); |
325 | /* Disable LCDIF clock gate. */ |
326 | CLOCK_DisableClock(kCLOCK_LcdPixel); |
327 | /* Set LCDIF_PRED. */ |
328 | CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1); |
329 | /* Set LCDIF_CLK_PODF. */ |
330 | CLOCK_SetDiv(kCLOCK_LcdifDiv, 3); |
331 | /* Set Lcdif pre clock source. */ |
332 | CLOCK_SetMux(kCLOCK_LcdifPreMux, 5); |
333 | /* Disable SPDIF clock gate. */ |
334 | CLOCK_DisableClock(kCLOCK_Spdif); |
335 | /* Set SPDIF0_CLK_PRED. */ |
336 | CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1); |
337 | /* Set SPDIF0_CLK_PODF. */ |
338 | CLOCK_SetDiv(kCLOCK_Spdif0Div, 7); |
339 | /* Set Spdif clock source. */ |
340 | CLOCK_SetMux(kCLOCK_SpdifMux, 3); |
341 | /* Disable Flexio1 clock gate. */ |
342 | CLOCK_DisableClock(kCLOCK_Flexio1); |
343 | /* Set FLEXIO1_CLK_PRED. */ |
344 | CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1); |
345 | /* Set FLEXIO1_CLK_PODF. */ |
346 | CLOCK_SetDiv(kCLOCK_Flexio1Div, 7); |
347 | /* Set Flexio1 clock source. */ |
348 | CLOCK_SetMux(kCLOCK_Flexio1Mux, 3); |
349 | /* Disable Flexio2 clock gate. */ |
350 | CLOCK_DisableClock(kCLOCK_Flexio2); |
351 | /* Set FLEXIO2_CLK_PRED. */ |
352 | CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1); |
353 | /* Set FLEXIO2_CLK_PODF. */ |
354 | CLOCK_SetDiv(kCLOCK_Flexio2Div, 7); |
355 | /* Set Flexio2 clock source. */ |
356 | CLOCK_SetMux(kCLOCK_Flexio2Mux, 3); |
357 | /* Set Pll3 sw clock source. */ |
358 | CLOCK_SetMux(kCLOCK_Pll3SwMux, 0); |
359 | /* Init ARM PLL. */ |
360 | CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); |
361 | /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd. |
362 | * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged. |
363 | * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/ |
364 | #ifndef SKIP_SYSCLK_INIT |
365 | #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) |
366 | #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged." |
367 | #endif |
368 | /* Init System PLL. */ |
369 | CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN); |
370 | /* Init System pfd0. */ |
371 | CLOCK_InitSysPfd(kCLOCK_Pfd0, 27); |
372 | /* Init System pfd1. */ |
373 | CLOCK_InitSysPfd(kCLOCK_Pfd1, 16); |
374 | /* Init System pfd2. */ |
375 | CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); |
376 | /* Init System pfd3. */ |
377 | CLOCK_InitSysPfd(kCLOCK_Pfd3, 16); |
378 | #endif |
379 | /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd. |
380 | * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged. |
381 | * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/ |
382 | #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) |
383 | /* Init Usb1 PLL. */ |
384 | CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN); |
385 | /* Init Usb1 pfd0. */ |
386 | CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33); |
387 | /* Init Usb1 pfd1. */ |
388 | CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16); |
389 | /* Init Usb1 pfd2. */ |
390 | CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17); |
391 | /* Init Usb1 pfd3. */ |
392 | CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19); |
393 | /* Disable Usb1 PLL output for USBPHY1. */ |
394 | CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; |
395 | #endif |
396 | /* DeInit Audio PLL. */ |
397 | CLOCK_DeinitAudioPll(); |
398 | /* Bypass Audio PLL. */ |
399 | CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1); |
400 | /* Set divider for Audio PLL. */ |
401 | CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK; |
402 | CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK; |
403 | /* Enable Audio PLL output. */ |
404 | CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK; |
405 | /* DeInit Video PLL. */ |
406 | CLOCK_DeinitVideoPll(); |
407 | /* Bypass Video PLL. */ |
408 | CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK; |
409 | /* Set divider for Video PLL. */ |
410 | CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0); |
411 | /* Enable Video PLL output. */ |
412 | CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK; |
413 | /* DeInit Enet PLL. */ |
414 | CLOCK_DeinitEnetPll(); |
415 | /* Bypass Enet PLL. */ |
416 | CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1); |
417 | /* Set Enet output divider. */ |
418 | CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1); |
419 | /* Enable Enet output. */ |
420 | CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK; |
421 | /* Set Enet2 output divider. */ |
422 | CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0); |
423 | /* Enable Enet2 output. */ |
424 | CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK; |
425 | /* Enable Enet25M output. */ |
426 | CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK; |
427 | /* DeInit Usb2 PLL. */ |
428 | CLOCK_DeinitUsb2Pll(); |
429 | /* Bypass Usb2 PLL. */ |
430 | CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1); |
431 | /* Enable Usb2 PLL output. */ |
432 | CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK; |
433 | /* Set preperiph clock source. */ |
434 | CLOCK_SetMux(kCLOCK_PrePeriphMux, 3); |
435 | /* Set periph clock source. */ |
436 | CLOCK_SetMux(kCLOCK_PeriphMux, 0); |
437 | /* Set periph clock2 clock source. */ |
438 | CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0); |
439 | /* Set per clock source. */ |
440 | CLOCK_SetMux(kCLOCK_PerclkMux, 0); |
441 | /* Set lvds1 clock source. */ |
442 | CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0); |
443 | /* Set clock out1 divider. */ |
444 | CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0); |
445 | /* Set clock out1 source. */ |
446 | CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1); |
447 | /* Set clock out2 divider. */ |
448 | CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0); |
449 | /* Set clock out2 source. */ |
450 | CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18); |
451 | /* Set clock out1 drives clock out1. */ |
452 | CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK; |
453 | /* Disable clock out1. */ |
454 | CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK; |
455 | /* Disable clock out2. */ |
456 | CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK; |
457 | /* Set SAI1 MCLK1 clock source. */ |
458 | IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); |
459 | /* Set SAI1 MCLK2 clock source. */ |
460 | IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0); |
461 | /* Set SAI1 MCLK3 clock source. */ |
462 | IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); |
463 | /* Set SAI2 MCLK3 clock source. */ |
464 | IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); |
465 | /* Set SAI3 MCLK3 clock source. */ |
466 | IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); |
467 | /* Set MQS configuration. */ |
468 | IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); |
469 | /* Set ENET Ref clock source. */ |
470 | IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK; |
471 | /* Set ENET2 Ref clock source. */ |
472 | IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK; |
473 | /* Set GPT1 High frequency reference clock source. */ |
474 | IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK; |
475 | /* Set GPT2 High frequency reference clock source. */ |
476 | IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK; |
477 | /* Set SystemCoreClock variable. */ |
478 | SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK; |
479 | } |
480 | |
481 | |