// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 *	Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/firmware/imx/rsrc.h>

audio_subsys: bus@59000000 {
	compatible = "simple-bus";
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0x59000000 0x0 0x59000000 0x1000000>;

	audio_ipg_clk: clock-audio-ipg {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <175000000>;
		clock-output-names = "audio_ipg_clk";
	};

	edma0: dma-controller@591F0000 {
		compatible = "fsl,imx8qm-edma";
		reg = <0x59200000 0x10000>, /* asrc0 */
			<0x59210000 0x10000>,
			<0x59220000 0x10000>,
			<0x59230000 0x10000>,
			<0x59240000 0x10000>,
			<0x59250000 0x10000>,
			<0x59260000 0x10000>, /* esai0 rx */
			<0x59270000 0x10000>, /* esai0 tx */
			<0x59280000 0x10000>, /* spdif0 rx */
			<0x59290000 0x10000>, /* spdif0 tx */
			<0x592c0000 0x10000>, /* sai0 rx */
			<0x592d0000 0x10000>, /* sai0 tx */
			<0x592e0000 0x10000>, /* sai1 rx */
			<0x592f0000 0x10000>, /* sai1 tx */
			<0x59300000 0x10000>, /* sai2 rx */
			<0x59310000 0x10000>, /* sai3 rx */
			<0x59350000 0x10000>,
			<0x59370000 0x10000>;
		#dma-cells = <3>;
		shared-interrupt;
		dma-channels = <18>;
		interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
				<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
				<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */
				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */
				<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */
				"edma0-chan2-rx", "edma0-chan3-tx",
				"edma0-chan4-tx", "edma0-chan5-tx",
				"edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */
				"edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */
				"edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */
				"edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */
				"edma0-chan16-rx", "edma0-chan17-rx", /* sai2, sai3 */
				"edma0-chan21-tx",              /* gpt5 */
				"edma0-chan23-rx";              /* gpt7 */
		power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
				<&pd IMX_SC_R_DMA_0_CH1>,
				<&pd IMX_SC_R_DMA_0_CH2>,
				<&pd IMX_SC_R_DMA_0_CH3>,
				<&pd IMX_SC_R_DMA_0_CH4>,
				<&pd IMX_SC_R_DMA_0_CH5>,
				<&pd IMX_SC_R_DMA_0_CH6>,
				<&pd IMX_SC_R_DMA_0_CH7>,
				<&pd IMX_SC_R_DMA_0_CH8>,
				<&pd IMX_SC_R_DMA_0_CH9>,
				<&pd IMX_SC_R_DMA_0_CH12>,
				<&pd IMX_SC_R_DMA_0_CH13>,
				<&pd IMX_SC_R_DMA_0_CH14>,
				<&pd IMX_SC_R_DMA_0_CH15>,
				<&pd IMX_SC_R_DMA_0_CH16>,
				<&pd IMX_SC_R_DMA_0_CH17>,
				<&pd IMX_SC_R_DMA_0_CH21>,
				<&pd IMX_SC_R_DMA_0_CH23>;
		power-domain-names = "edma0-chan0", "edma0-chan1",
				     "edma0-chan2", "edma0-chan3",
				     "edma0-chan4", "edma0-chan5",
				     "edma0-chan6", "edma0-chan7",
				     "edma0-chan8", "edma0-chan9",
				     "edma0-chan12", "edma0-chan13",
				     "edma0-chan14", "edma0-chan15",
				     "edma0-chan16", "edma0-chan17",
				     "edma0-chan21", "edma0-chan23";
		status = "okay";
	};

	edma1: dma-controller@599F0000 {
		compatible = "fsl,imx8qm-edma";
		reg = <0x59A00000 0x10000>, /* asrc1 */
			<0x59A10000 0x10000>,
			<0x59A20000 0x10000>,
			<0x59A30000 0x10000>,
			<0x59A40000 0x10000>,
			<0x59A50000 0x10000>,
			<0x59A80000 0x10000>, /* sai4 rx */
			<0x59A90000 0x10000>, /* sai4 tx */
			<0x59AA0000 0x10000>; /* sai5 tx */
		#dma-cells = <3>;
		shared-interrupt;
		dma-channels = <9>;
		interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */
				<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
		interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */
				"edma1-chan2-rx", "edma1-chan3-tx",
				"edma1-chan4-tx", "edma1-chan5-tx",
				"edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */
				"edma1-chan10-tx";                 /* sai5 */
		power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
				<&pd IMX_SC_R_DMA_1_CH1>,
				<&pd IMX_SC_R_DMA_1_CH2>,
				<&pd IMX_SC_R_DMA_1_CH3>,
				<&pd IMX_SC_R_DMA_1_CH4>,
				<&pd IMX_SC_R_DMA_1_CH5>,
				<&pd IMX_SC_R_DMA_1_CH8>,
				<&pd IMX_SC_R_DMA_1_CH9>,
				<&pd IMX_SC_R_DMA_1_CH10>;
		power-domain-names = "edma1-chan0", "edma1-chan1",
				     "edma1-chan2", "edma1-chan3",
				     "edma1-chan4", "edma1-chan5",
				     "edma1-chan8", "edma1-chan9",
				     "edma1-chan10";
		status = "okay";
	};

	acm: acm@59e00000 {
		compatible = "nxp,imx8qxp-acm";
		reg = <0x59e00000 0x1D0000>;
		#clock-cells = <1>;
		power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
				<&pd IMX_SC_R_AUDIO_CLK_1>,
				<&pd IMX_SC_R_MCLK_OUT_0>,
				<&pd IMX_SC_R_MCLK_OUT_1>,
				<&pd IMX_SC_R_AUDIO_PLL_0>,
				<&pd IMX_SC_R_AUDIO_PLL_1>,
				<&pd IMX_SC_R_ASRC_0>,
				<&pd IMX_SC_R_ASRC_1>,
				<&pd IMX_SC_R_ESAI_0>,
				<&pd IMX_SC_R_SAI_0>,
				<&pd IMX_SC_R_SAI_1>,
				<&pd IMX_SC_R_SAI_2>,
				<&pd IMX_SC_R_SAI_3>,
				<&pd IMX_SC_R_SAI_4>,
				<&pd IMX_SC_R_SAI_5>,
				<&pd IMX_SC_R_SPDIF_0>,
				<&pd IMX_SC_R_MQS_0>;
	};

	asrc0: asrc@59000000 {
		compatible = "fsl,imx8qm-asrc0";
		reg = <0x59000000 0x10000>;
		interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&asrc0_lpcg 0>,
			<&asrc0_lpcg 0>,
			<&aud_pll_div0_lpcg 0>,
			<&aud_pll_div1_lpcg 0>,
			<&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
			<&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>;
		clock-names = "ipg", "mem",
			"asrck_0", "asrck_1", "asrck_2", "asrck_3",
			"asrck_4", "asrck_5", "asrck_6", "asrck_7",
			"asrck_8", "asrck_9", "asrck_a", "asrck_b",
			"asrck_c", "asrck_d", "asrck_e", "asrck_f",
			"spba";
		dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>,
			<&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>;
		dma-names = "rxa", "rxb", "rxc",
				"txa", "txb", "txc";
		fsl,asrc-rate  = <8000>;
		fsl,asrc-width = <16>;
		power-domains = <&pd IMX_SC_R_ASRC_0>;
		status = "disabled";
        };

	esai0: esai@59010000 {
		compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai";
		reg = <0x59010000 0x10000>;
		interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&esai0_lpcg 1>,
			<&esai0_lpcg 0>,
			<&esai0_lpcg 1>,
			<&clk_dummy>;
		clock-names = "core", "extal", "fsys", "spba";
		dmas = <&edma0 6 0 1>, <&edma0 7 0 0>;
		dma-names = "rx", "tx";
		power-domains = <&pd IMX_SC_R_ESAI_0>;
		status = "disabled";
	};

	spdif0: spdif@59020000 {
		compatible = "fsl,imx8qm-spdif";
		reg = <0x59020000 0x10000>;
		interrupts =  <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
			<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
		clocks = <&spdif0_lpcg 1>, /* core */
			<&clk_dummy>, /* rxtx0 */
			<&spdif0_lpcg 0>, /* rxtx1 */
			<&clk_dummy>, /* rxtx2 */
			<&clk_dummy>, /* rxtx3 */
			<&clk_dummy>, /* rxtx4 */
			<&audio_ipg_clk>, /* rxtx5 */
			<&clk_dummy>, /* rxtx6 */
			<&clk_dummy>, /* rxtx7 */
			<&clk_dummy>; /* spba */
		clock-names = "core", "rxtx0",
				"rxtx1", "rxtx2",
				"rxtx3", "rxtx4",
				"rxtx5", "rxtx6",
				"rxtx7", "spba";
		dmas = <&edma0 8 0 5>, <&edma0 9 0 4>;
		dma-names = "rx", "tx";
		power-domains = <&pd IMX_SC_R_SPDIF_0>;
		status = "disabled";
	};

	spdif1: spdif@59030000 {
		compatible = "fsl,imx8qm-spdif";
		reg = <0x59030000 0x10000>;
		interrupts =  <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, /* rx */
			     <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; /* tx */
		clocks = <&spdif1_lpcg 1>, /* core */
			<&clk_dummy>, /* rxtx0 */
			<&spdif1_lpcg 0>, /* rxtx1 */
			<&clk_dummy>, /* rxtx2 */
			<&clk_dummy>, /* rxtx3 */
			<&clk_dummy>, /* rxtx4 */
			<&audio_ipg_clk>, /* rxtx5 */
			<&clk_dummy>, /* rxtx6 */
			<&clk_dummy>, /* rxtx7 */
			<&clk_dummy>; /* spba */
		clock-names = "core", "rxtx0",
			      "rxtx1", "rxtx2",
			      "rxtx3", "rxtx4",
			      "rxtx5", "rxtx6",
			      "rxtx7", "spba";
		dmas = <&edma0 10 0 5>, <&edma0 11 0 4>;
		dma-names = "rx", "tx";
		power-domains = <&pd IMX_SC_R_SPDIF_1>;
		status = "disabled";
	};

	sai0: sai@59040000 {
		compatible = "fsl,imx8qm-sai";
		reg = <0x59040000 0x10000>;
		interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&sai0_lpcg 1>,
			<&clk_dummy>,
			<&sai0_lpcg 0>,
			<&clk_dummy>,
			<&clk_dummy>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dma-names = "rx", "tx";
		dmas = <&edma0 12 0 1>, <&edma0 13 0 0>;
		power-domains = <&pd IMX_SC_R_SAI_0>;
		status = "disabled";
	};

	sai1: sai@59050000 {
		compatible = "fsl,imx8qm-sai";
		reg = <0x59050000 0x10000>;
		interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&sai1_lpcg 1>,
			<&clk_dummy>,
			<&sai1_lpcg 0>,
			<&clk_dummy>,
			<&clk_dummy>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dma-names = "rx", "tx";
		dmas = <&edma0 14 0 1>, <&edma0 15 0 0>;
		power-domains = <&pd IMX_SC_R_SAI_1>;
		status = "disabled";
	};

	sai2: sai@59060000 {
		compatible = "fsl,imx8qm-sai";
		reg = <0x59060000 0x10000>;
		interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&sai2_lpcg 1>,
			<&clk_dummy>,
			<&sai2_lpcg 0>,
			<&clk_dummy>,
			<&clk_dummy>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dma-names = "rx";
		dmas = <&edma0 16 0 1>;
		power-domains = <&pd IMX_SC_R_SAI_2>;
		status = "disabled";
	};

	sai3: sai@59070000 {
		compatible = "fsl,imx8qm-sai";
		reg = <0x59070000 0x10000>;
		interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&sai3_lpcg 1>,
			<&clk_dummy>,
			<&sai3_lpcg 0>,
			<&clk_dummy>,
			<&clk_dummy>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dma-names = "rx";
		dmas = <&edma0 17 0 1>;
		power-domains = <&pd IMX_SC_R_SAI_3>;
		status = "disabled";
	};

	asrc1: asrc@59800000 {
		compatible = "fsl,imx8qm-asrc1";
		reg = <0x59800000 0x10000>;
		interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&asrc1_lpcg 0>,
			<&asrc1_lpcg 0>,
			<&aud_pll_div0_lpcg 0>,
			<&aud_pll_div1_lpcg 0>,
			<&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
			<&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>,
			<&clk_dummy>;
		clock-names = "ipg", "mem",
			"asrck_0", "asrck_1", "asrck_2", "asrck_3",
			"asrck_4", "asrck_5", "asrck_6", "asrck_7",
			"asrck_8", "asrck_9", "asrck_a", "asrck_b",
			"asrck_c", "asrck_d", "asrck_e", "asrck_f",
			"spba";
		dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>,
			<&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>;
		dma-names = "rxa", "rxb", "rxc",
				"txa", "txb", "txc";
		fsl,asrc-rate  = <8000>;
		fsl,asrc-width = <16>;
		power-domains = <&pd IMX_SC_R_ASRC_1>;
		status = "disabled";
	};

	sai4: sai@59820000 {
		compatible = "fsl,imx8qm-sai";
		reg = <0x59820000 0x10000>;
		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&sai4_lpcg 1>,
			<&clk_dummy>,
			<&sai4_lpcg 0>,
			<&clk_dummy>,
			<&clk_dummy>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dma-names = "rx", "tx";
		dmas = <&edma1 8 0 1>, <&edma1 9 0 0>;
		power-domains = <&pd IMX_SC_R_SAI_4>;
		status = "disabled";
	};

	sai5: sai@59830000 {
		compatible = "fsl,imx8qm-sai";
		reg = <0x59830000 0x10000>;
		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&sai5_lpcg 1>,
			<&clk_dummy>,
			<&sai5_lpcg 0>,
			<&clk_dummy>,
			<&clk_dummy>;
		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
		dma-names = "tx";
		dmas = <&edma1 10 0 0>;
		power-domains = <&pd IMX_SC_R_SAI_5>;
		status = "disabled";
	};

	amix: amix@59840000 {
		compatible = "fsl,imx8qm-audmix";
		reg = <0x59840000 0x10000>;
		clocks = <&amix_lpcg 0>;
		clock-names = "ipg";
		power-domains = <&pd IMX_SC_R_AMIX>;
		dais = <&sai4>, <&sai5>;
		status = "disabled";
	};

	mqs: mqs@59850000 {
		compatible = "fsl,imx8qm-mqs";
		reg = <0x59850000 0x10000>;
		clocks = <&mqs0_lpcg 1>,
			<&mqs0_lpcg 0>;
		clock-names = "core", "mclk";
		power-domains = <&pd IMX_SC_R_MQS_0>;
		status = "disabled";
	};

	asrc0_lpcg: clock-controller@59400000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59400000 0x10000>;
		#clock-cells = <1>;
		clocks = <&audio_ipg_clk>;
		bit-offset = <16>;
		clock-output-names = "asrc0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_ASRC_0>;
	};

	esai0_lpcg: clock-controller@59410000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59410000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "esai0_lpcg_extal_clk",
				     "esai0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_ESAI_0>;
	};

	spdif0_lpcg: clock-controller@59420000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59420000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "spdif0_lpcg_tx_clk",
				     "spdif0_lpcg_gclkw";
		power-domains = <&pd IMX_SC_R_SPDIF_0>;
	};

	spdif1_lpcg: clock-controller@59430000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59430000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "spdif1_lpcg_tx_clk",
				     "spdif1_lpcg_gclkw";
		power-domains = <&pd IMX_SC_R_SPDIF_1>;
		status = "disabled";
	};

	sai0_lpcg: clock-controller@59440000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59440000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_SAI0_MCLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "sai0_lpcg_mclk",
				     "sai0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SAI_0>;
	};

	sai1_lpcg: clock-controller@59450000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59450000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_SAI1_MCLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "sai1_lpcg_mclk",
				     "sai1_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SAI_1>;
	};

	sai2_lpcg: clock-controller@59460000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59460000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_SAI2_MCLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "sai2_lpcg_mclk",
				     "sai2_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SAI_2>;
	};

	sai3_lpcg: clock-controller@59470000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59470000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_SAI3_MCLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "sai3_lpcg_mclk",
				     "sai3_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SAI_3>;
	};

	dsp_lpcg: clock-controller@59580000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59580000 0x10000>;
		#clock-cells = <1>;
		clocks = <&audio_ipg_clk>,
			 <&audio_ipg_clk>,
			 <&audio_ipg_clk>;
		bit-offset = <16 20 28>;
		clock-output-names = "dsp_lpcg_adb_aclk",
				     "dsp_lpcg_ipg_clk",
				     "dsp_lpcg_core_clk";
		power-domains = <&pd IMX_SC_R_DSP>;
	};

	dsp_ram_lpcg: clock-controller@59590000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59590000 0x10000>;
		#clock-cells = <1>;
		clocks = <&audio_ipg_clk>;
		bit-offset = <16>;
		clock-output-names = "dsp_ram_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_DSP_RAM>;
	};

	asrc1_lpcg: clock-controller@59c00000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59c00000 0x10000>;
		#clock-cells = <1>;
		clocks = <&audio_ipg_clk>;
		bit-offset = <16>;
		clock-output-names = "asrc1_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_ASRC_1>;
	};

	sai4_lpcg: clock-controller@59c20000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59c20000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "sai4_lpcg_mclk",
				     "sai4_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SAI_4>;
	};

	sai5_lpcg: clock-controller@59c30000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59c30000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "sai5_lpcg_mclk",
				     "sai5_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_SAI_5>;
	};

	amix_lpcg: clock-controller@59c40000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59c40000 0x10000>;
		#clock-cells = <1>;
		clocks = <&audio_ipg_clk>;
		bit-offset = <0>;
		clock-output-names = "amix_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_AMIX>;
	};

	mqs0_lpcg: clock-controller@59c50000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59c50000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>,
			 <&audio_ipg_clk>;
		bit-offset = <0 16>;
		clock-output-names = "mqs0_lpcg_mclk",
				     "mqs0_lpcg_ipg_clk";
		power-domains = <&pd IMX_SC_R_MQS_0>;
	};

	aud_rec0_lpcg: clock-controller@59d00000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59d00000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
		bit-offset = <0>;
		clock-output-names = "aud_rec_clk0_lpcg_clk";
		power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;
	};

	aud_rec1_lpcg: clock-controller@59d10000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59d10000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>;
		bit-offset = <0>;
		clock-output-names = "aud_rec_clk1_lpcg_clk";
		power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;
	};

	aud_pll_div0_lpcg: clock-controller@59d20000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59d20000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>;
		bit-offset = <0>;
		clock-output-names = "aud_pll_div_clk0_lpcg_clk";
		power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;
	};

	aud_pll_div1_lpcg: clock-controller@59d30000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59d30000 0x10000>;
		#clock-cells = <1>;
		clocks = <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>;
		bit-offset = <0>;
		clock-output-names = "aud_pll_div_clk1_lpcg_clk";
		power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;
	};

	mclkout0_lpcg: clock-controller@59d50000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59d50000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_MCLKOUT0_SEL>;
		bit-offset = <0>;
		clock-output-names = "mclkout0_lpcg_clk";
		power-domains = <&pd IMX_SC_R_MCLK_OUT_0>;
	};

	mclkout1_lpcg: clock-controller@59d60000 {
		compatible = "fsl,imx8qxp-lpcg";
		reg = <0x59d60000 0x10000>;
		#clock-cells = <1>;
		clocks = <&acm IMX_ADMA_ACM_MCLKOUT1_SEL>;
		bit-offset = <0>;
		clock-output-names = "mclkout1_lpcg_clk";
		power-domains = <&pd IMX_SC_R_MCLK_OUT_1>;
	};
};
