// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2019 NXP
 */

/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/reset/imx8mp-mediamix.h>
#include <dt-bindings/reset/imx-hdmimix-reset.h>
#include "imx8mp-pinfunc.h"

/ {
	model = "Freescale i.MX8MP EVK";
	compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		mmc2 = &usdhc3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		A53_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			clock-latency = <61036>; /* two CLK32 periods */
			next-level-cache = <&A53_L2>;
			enable-method = "psci";
			#cooling-cells = <2>;
		};

		A53_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			clock-latency = <61036>; /* two CLK32 periods */
			next-level-cache = <&A53_L2>;
			enable-method = "psci";
			#cooling-cells = <2>;
		};

		A53_L2: l2-cache0 {
			compatible = "cache";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	gic: interrupt-controller@38800000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
		      <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
		clock-frequency = <8333333>;
	};

	clk_dummy: clock@7 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "clk_dummy";
	};

	/* The clocks are configured by 1st OS */
	clk_400m: clock@8 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <200000000>;
		clock-output-names = "200m";
	};

	clk_266m: clock@9 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <266000000>;
		clock-output-names = "266m";
	};
// JH: UART4 
	osc_24m: clock@1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc_24m";
	}; 
	osc_32k: clock-osc-32k {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "osc_32k";
	};
	clk_ext1: clock-ext1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext1";
	};

	clk_ext2: clock-ext2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext2";
	};

	clk_ext3: clock-ext3 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <133000000>;
		clock-output-names = "clk_ext3";
	};

	clk_ext4: clock-ext4 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency= <133000000>;
		clock-output-names = "clk_ext4";
	};

	power-domains {
	compatible = "simple-bus";

	mipi_phy1_pd: mipiphy1-pd {
		compatible = "fsl,imx8m-pm-domain";
		#power-domain-cells = <0>;
		domain-index = <15>;
		domain-name = "mipi_phy1";
		parent-domains = <&mediamix_pd>;
	};
	mediamix_pd: mediamix-pd {
		compatible = "fsl,imx8m-pm-domain";
		#power-domain-cells = <0>;
		domain-index = <13>;
		domain-name = "mediamix";
		clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
			 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
		};
	};

	pci@fd700000 {
		compatible = "pci-host-ecam-generic";
		device_type = "pci";
		bus-range = <0 0>;
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_EDGE_RISING>,
				<0 0 0 2 &gic GIC_SPI 155 IRQ_TYPE_EDGE_RISING>,
				<0 0 0 3 &gic GIC_SPI 156 IRQ_TYPE_EDGE_RISING>,
				<0 0 0 4 &gic GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
		reg = <0x0 0xfd700000 0x0 0x100000>;
		ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x0 0x3e000000>;

		aips3: bus@30800000 {
			compatible = "simple-bus";
			reg = <0x30800000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			uart4: serial@30a60000 {
				compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
				reg = <0x30a60000 0x10000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};
			usdhc3: mmc@30b60000 {
				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
				reg = <0x30b60000 0x10000>;
				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				fsl,tuning-start-tap = <20>;
				fsl,tuning-step= <2>;
				status = "disabled";
			};
			i2c3: i2c@30a40000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
				reg = <0x30a40000 0x10000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
				status = "disabled";
			};
		};
		aips1: bus@30000000 {
			compatible = "simple-bus";
			reg = <0x30000000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			
			gpio5: gpio@30240000 {
				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
				reg = <0x30240000 0x10000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};
			gpio2: gpio@30210000 {
				compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
				reg = <0x30210000 0x10000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
			};			
			iomuxc: pinctrl@30330000 {
				compatible = "fsl,imx8mp-iomuxc";
				reg = <0x30330000 0x10000>;
			};
			clk: clock-controller@30380000 {
				compatible = "fsl,imx8mp-ccm";
				reg = <0x30380000 0x10000>;
				#clock-cells = <1>;
				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
					 <&clk_ext3>, <&clk_ext4>;
				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
					      "clk_ext3", "clk_ext4";
				assigned-clocks = <&clk IMX8MP_CLK_NOC>,
						  <&clk IMX8MP_CLK_NOC_IO>,
						  <&clk IMX8MP_CLK_GIC>,
						  <&clk IMX8MP_CLK_AUDIO_AHB>,
						  <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
						  <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
						  <&clk IMX8MP_AUDIO_PLL1>,
						  <&clk IMX8MP_AUDIO_PLL2>,
						  <&clk IMX8MP_VIDEO_PLL1>;
				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
							 <&clk IMX8MP_SYS_PLL1_800M>,
							 <&clk IMX8MP_SYS_PLL2_500M>,
							 <&clk IMX8MP_SYS_PLL1_800M>,
							 <&clk IMX8MP_SYS_PLL1_800M>;
				assigned-clock-rates = <1000000000>,
						       <800000000>,
						       <500000000>,
						       <400000000>,
						       <800000000>,
						       <400000000>,
						       <393216000>,
						       <361267200>,
						       <1039500000>;
			};
		};
		aips4: bus@32c00000 {
			compatible = "simple-bus";
			reg = <0x32c00000 0x400000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			mipi_dsi: mipi_dsi@32e60000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mp-mipi-dsim";
				reg = <0x32e60000 0x10000>;
				clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
					 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
				clock-names = "cfg", "pll-ref";
				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
				assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
				assigned-clock-rates = <12000000>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&mipi_phy1_pd>;
				blk-ctl = <&mediamix_blk_ctl>;
				status = "disabled";

				port@0 {
					dsim_from_lcdif: endpoint {
						remote-endpoint = <&lcdif_to_dsim>;
					};
				};
			};
			lcdif1: lcd-controller@32e80000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx8mp-lcdif1";
				reg = <0x32e80000 0x10000>;
				clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
					 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
				clock-names = "pix", "disp-axi", "disp-apb";
				assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
						  <&clk IMX8MP_CLK_MEDIA_AXI>,
						  <&clk IMX8MP_CLK_MEDIA_APB>;
				assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>,
							 <&clk IMX8MP_SYS_PLL2_1000M>,
							 <&clk IMX8MP_SYS_PLL1_800M>;
				assigned-clock-rates = <0>, <500000000>, <200000000>;
				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
				blk-ctl = <&mediamix_blk_ctl>;
				power-domains = <&mediamix_pd>;
				status = "disabled";

				lcdif1_disp: port@0 {
					reg = <0>;

					lcdif_to_dsim: endpoint {
						remote-endpoint = <&dsim_from_lcdif>;
					};
				};
			};
			mediamix_blk_ctl: blk-ctl@32ec0000 {
				compatible = "fsl,imx8mp-mediamix-blk-ctl",
					     "syscon";
				reg = <0x32ec0000 0x10000>;
				clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
			};			
		};
	};
};
	
&usdhc3 {
	clocks = <&clk_dummy>,
		<&clk_266m>,
		<&clk_400m>;
	clock-names = "ipg", "ahb", "per";
	bus-width = <8>;
	non-removable;
	status = "okay";
};

//JH:LCD 
&lcdif1 {
	status = "okay";
};


&mipi_dsi {
        status = "okay";

        port@1 {
                mipi_dsi_out: endpoint {
                        remote-endpoint = <&dsi_lvds_bridge_in>;
                        attach-bridge;
                };
        };

};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x400001c3
				MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x40000019
				MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07			0x400001c3
				MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12			0x400001c3
			>;
		};	
		pinctrl_i2c3: i2c3grp {
			fsl,pins = <
				MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL			0x400001c3
				MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA			0x400001c3
			>;
		};
		pinctrl_mipi_touch: touchgrp {
			fsl,pins = <
				MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 		0x154
			>;
		};		
	};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
        dsi_lvds_bridge: sn65dsi83@2d {
                compatible = "ti,sn65dsi83";
                reg = <0x2d>;
                ti,dsi-lanes = <4>;
                ti,lvds-format = <1>;
                ti,lvds-bpp = <24>;
                ti,width-mm = <177>;
                ti,height-mm = <100>;
                enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
                interrupt-parent = <&gpio2>;
                interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
                status = "okay";

                display-timings {
                        lvds {
                                //clock-frequency = <62500000>;
                                clock-frequency = <71150000>;
                                hactive = <1280>;
                                vactive = <720>;
                                hback-porch = <120>;
                                hfront-porch = <120>;
                                vback-porch = <25>;
                                vfront-porch = <25>;
                                //hsync-len = <30>;
                                hsync-len = <2>;
                                //vsync-len = <5>;
                                vsync-len = <1>;
                                hsync-active = <0>; 
                                vsync-active = <0>;
                                de-active = <1>;
                                pixelclk-active = <0>;
                        };
                };

                port {
                        dsi_lvds_bridge_in: endpoint {
                                remote-endpoint = <&mipi_dsi_out>;
                        };
                };
        };

	
	touchscreenmipi@41 {
		compatible = "ilitek,ili251x";
		reg = <0x41>;
		pinctrl-0 = <&pinctrl_mipi_touch>;
		interrupt-parent = <&gpio5>;
		interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
		//reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
	};
};


//JH:UART4
&uart4 {
	clocks = <&osc_24m>,
		<&osc_24m>;
	clock-names = "ipg", "per";
	status = "okay";
};