diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index e635702..319c023 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -21,6 +21,7 @@
 
 #include <linux/netdevice.h>
 #include <linux/can.h>
+#include <linux/debugfs.h>
 #include <linux/can/dev.h>
 #include <linux/can/error.h>
 #include <linux/can/led.h>
@@ -66,7 +67,11 @@
 #define FLEXCAN_MCR_BCC			BIT(16)
 #define FLEXCAN_MCR_LPRIO_EN		BIT(13)
 #define FLEXCAN_MCR_AEN			BIT(12)
-#define FLEXCAN_MCR_MAXMB(x)		((x) & 0x7f)
+/* set MAXMB as 20 (see table 24-21 of RM) as we use 
+* MB0-19 for Rx FIFO and MB20 for Tx; RFFN is set to 
+* 0x6 which is < MAXMB
+*/
+#define FLEXCAN_MCR_MAXMB(x)		((x) & 0x14)
 #define FLEXCAN_MCR_IDAM_A		(0 << 8)
 #define FLEXCAN_MCR_IDAM_B		(1 << 8)
 #define FLEXCAN_MCR_IDAM_C		(2 << 8)
@@ -152,8 +157,12 @@
 
 /* FLEXCAN interrupt flag register (IFLAG) bits */
 /* Errata ERR005829 step7: Reserve first valid MB */
-#define FLEXCAN_TX_BUF_RESERVED		8
-#define FLEXCAN_TX_BUF_ID		9
+#define FLEXCAN_TX_BUF_RESERVED		20/* using this as 20 as we use RFFN = 0x6; so the first available one is MB20 */
+/* use the 21st MB as we are using RFFN as 0x6 meaning
+* message buffers occupied by Rx FIFO and ID Filter
+* table 24-21 uses MB0-19; we dont use MB20 as well in view of errata 5829
+*/
+#define FLEXCAN_TX_BUF_ID		21
 #define FLEXCAN_IFLAG_BUF(x)		BIT(x)
 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW	BIT(7)
 #define FLEXCAN_IFLAG_RX_FIFO_WARN	BIT(6)
@@ -297,6 +306,62 @@ static const struct can_bittiming_const flexcan_bittiming_const = {
 	.brp_inc = 1,
 };
 
+u32 can_ids_rx_filtering[] = {
+	0x18EAFF00, /* PGN Request Global 		*/
+	0x18EA4C00, /* PGN Request Unicast 		*/
+	0x18C9FF00, /* Request2 Global 			*/
+	0x18C94C00, /* Request2 Unicast 		*/
+	0x1CEBFF00, /* TP.DT Global 			*/
+	0x1CEB4C00, /* TP.DT Unicast 			*/
+	0x1CC7FF00, /* ETP.DT Global 			*/
+	0x1CC74C00, /* ETP.DT Unicast 			*/
+	0x1CECFF00, /* TP.CM Global 			*/
+	0x1CEC4C00, /* TP.CM Unicast 			*/
+	0x1CC8FF00, /* ETP.CM Global 			*/
+	0x1CC84C00, /* ETP.CM Unicast 			*/
+	0x1CE34C00, /* PITS 					*/
+	0x18D0FF00, /* Dimming Global 			*/
+	0x18D04C00, /* Dimming Unicast 			*/
+	0x18FFFE00, /* FFFE commands 			*/
+	0x1CFFFE00, /* FFFE commands 			*/
+	0x0CFFFE00, /* FFFE commands 			*/
+	0x18FFF800, /* FFF8 commands 			*/
+	0x0CFF2800, /* FFF8 commands 			*/
+	0x18EF4C00, /* EFXX commands Unicast 	*/
+	0x18EFFF00, /* EFXX commands Global 	*/
+	0x1CEF4C00, /* EFXX commands Unicast 	*/
+	0x1CEFFF00, /* EFXX commands Global 	*/
+	0x18EEFF00, /* Address Claim 			*/
+	0x18D54C00, /* Time date adjust Unicast */
+	0x18D5FF00, /* Time date adjust Global 	*/
+	0x18FEE600, /* Time date 				*/
+	0x18FEF100, /* CCVS 					*/
+	0x18F00500, /* ETC2 					*/
+	0x18FE0F00, /* Language Command 		*/
+	0x0CFDCC00, /* External Lights Control 	*/
+	0x18DF4C00, /* DM13 Unicast 			*/
+	0x18DFFF00, /* DM13 Global 				*/
+	0x18D94C00, /* DM14 Unicast 			*/
+	0x18D9FF00, /* DM14 Global 				*/
+	0x18D84C00, /* DM15 Unicast 			*/
+	0x18D8FF00, /* DM15 Global 				*/
+	0x18D74C00, /* DM16 Unicast 			*/
+	0x18D7FF00, /* DM16 Global 				*/
+	0x18D64C00, /* DM17 Unicast 			*/
+	0x18D6FF00, /* DM17 Global 				*/
+	0x18DA4C00, /* UDS Physical Unicast 	*/
+	0x18DAFF00, /* UDS Physical Global 		*/
+	0x18DB4C00, /* UDS Functional Unicast 	*/
+	0x18DBFF00, /* UDS Functional Global 	*/
+	0x18FF0000, /* SCA C2 					*/
+	0x18FF0500, /* ICUC C7 					*/
+	0x14FF0100, /* MSF C1 					*/
+	0x11F00700, /* LDWS 					*/
+	0x0CFF2700, /* VP39 					*/
+	0x0CFF2600, /* VP38 					*/
+	0x0CFF2F00  /* VP47 					*//*53-Filters*/
+};
+
 /*
  * Abstract off the read/write for arm versus ppc. This
  * assumes that PPC uses big-endian registers and everything
@@ -889,12 +954,22 @@ static int flexcan_chip_start(struct net_device *dev)
 	reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
 	reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
 		FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
-		FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
+		FLEXCAN_MCR_IDAM_A | FLEXCAN_MCR_SRX_DIS |
 		FLEXCAN_MCR_WAK_MSK | FLEXCAN_MCR_SLF_WAK |
 		FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
+
+	reg_mcr &= ~(1<<16); /* IRMQ set to 0; individual Rx masking and queue feature disabled*/
+
 	netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
 	flexcan_write(reg_mcr, &regs->mcr);
 
+	/* MB occupied by Rx FIFO and ID Filter Table => MB0-19 */
+	reg_crl2 = flexcan_read(&regs->crl2);
+	
+	reg_crl2 |= (0x6 << 24); /* RFFN is 0x6 56-Rx FIFO filters */
+	reg_crl2 &= ~(0x1 << 18); /* set MRP to 0; matching starts from Rx FIFO */
+
+	flexcan_write(reg_crl2, &regs->crl2);
 	/*
 	 * CTRL
 	 *
@@ -941,13 +1016,169 @@ static int flexcan_chip_start(struct net_device *dev)
 	flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
 		      &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
 
-	/* acceptance mask/acceptance code (accept everything) */
-	flexcan_write(0x0, &regs->rxgmask);
-	flexcan_write(0x0, &regs->rx14mask);
-	flexcan_write(0x0, &regs->rx15mask);
-
-	if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
-		flexcan_write(0x0, &regs->rxfgmask);
+	/* set the CAN IDs as filter (we have 53-ROC+JD filters) */
+
+	flexcan_write(0x0, &regs->cantxfg[6].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[0] << 1), &regs->cantxfg[6].can_ctrl);
+	
+	flexcan_write(0x0, &regs->cantxfg[6].can_id);
+	flexcan_write((can_ids_rx_filtering[1] << 1), &regs->cantxfg[6].can_id);
+
+	flexcan_write(0x0, &regs->cantxfg[6].data[0]);
+	flexcan_write((can_ids_rx_filtering[2] << 1), &regs->cantxfg[6].data[0]);
+	
+	flexcan_write(0x0, &regs->cantxfg[6].data[1]);
+	flexcan_write((can_ids_rx_filtering[3] << 1), &regs->cantxfg[6].data[1]);
+	
+	flexcan_write(0x0, &regs->cantxfg[7].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[4] << 1), &regs->cantxfg[7].can_ctrl);
+	
+	flexcan_write(0x0, &regs->cantxfg[7].can_id);
+	flexcan_write((can_ids_rx_filtering[5] << 1), &regs->cantxfg[7].can_id);
+	
+	flexcan_write(0x0, &regs->cantxfg[7].data[0]);
+	flexcan_write((can_ids_rx_filtering[6] << 1), &regs->cantxfg[7].data[0]);
+	
+	flexcan_write(0x0, &regs->cantxfg[7].data[1]);
+	flexcan_write((can_ids_rx_filtering[7] << 1), &regs->cantxfg[7].data[1]);
+	
+	flexcan_write(0x0, &regs->cantxfg[8].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[8] << 1), &regs->cantxfg[8].can_ctrl);
+		
+	flexcan_write(0x0, &regs->cantxfg[8].can_id);
+	flexcan_write((can_ids_rx_filtering[9] << 1), &regs->cantxfg[8].can_id);
+
+	flexcan_write(0x0, &regs->cantxfg[8].data[0]);
+	flexcan_write((can_ids_rx_filtering[10] << 1), &regs->cantxfg[8].data[0]);
+	
+	flexcan_write(0x0, &regs->cantxfg[8].data[1]);
+	flexcan_write((can_ids_rx_filtering[11] << 1), &regs->cantxfg[8].data[1]);
+
+	flexcan_write(0x0, &regs->cantxfg[9].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[12] << 1), &regs->cantxfg[9].can_ctrl);
+	
+	flexcan_write(0x0, &regs->cantxfg[9].can_id);
+	flexcan_write((can_ids_rx_filtering[13] << 1), &regs->cantxfg[9].can_id);
+	
+	flexcan_write(0x0, &regs->cantxfg[9].data[0]);
+	flexcan_write((can_ids_rx_filtering[14] << 1), &regs->cantxfg[9].data[0]);
+	
+	flexcan_write(0x0, &regs->cantxfg[9].data[1]);
+	flexcan_write((can_ids_rx_filtering[15] << 1), &regs->cantxfg[9].data[1]);
+	
+	flexcan_write(0x0, &regs->cantxfg[10].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[16] << 1), &regs->cantxfg[10].can_ctrl);
+		
+	flexcan_write(0x0, &regs->cantxfg[10].can_id);
+	flexcan_write((can_ids_rx_filtering[17] << 1), &regs->cantxfg[10].can_id);
+
+	flexcan_write(0x0, &regs->cantxfg[10].data[0]);
+	flexcan_write((can_ids_rx_filtering[18] << 1), &regs->cantxfg[10].data[0]);
+	
+	flexcan_write(0x0, &regs->cantxfg[10].data[1]);
+	flexcan_write((can_ids_rx_filtering[19] << 1), &regs->cantxfg[10].data[1]);
+
+	flexcan_write(0x0, &regs->cantxfg[11].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[20] << 1), &regs->cantxfg[11].can_ctrl);
+	
+	flexcan_write(0x0, &regs->cantxfg[11].can_id);
+	flexcan_write((can_ids_rx_filtering[21] << 1), &regs->cantxfg[11].can_id);
+
+	flexcan_write(0x0, &regs->cantxfg[11].data[0]);
+	flexcan_write((can_ids_rx_filtering[22] << 1), &regs->cantxfg[11].data[0]);
+	
+	flexcan_write(0x0, &regs->cantxfg[11].data[1]);
+	flexcan_write((can_ids_rx_filtering[23] << 1), &regs->cantxfg[11].data[1]);
+	
+	flexcan_write(0x0, &regs->cantxfg[12].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[24] << 1), &regs->cantxfg[12].can_ctrl);
+	
+	flexcan_write(0x0, &regs->cantxfg[12].can_id);
+	flexcan_write((can_ids_rx_filtering[25] << 1), &regs->cantxfg[12].can_id);
+	
+	flexcan_write(0x0, &regs->cantxfg[12].data[0]);
+	flexcan_write((can_ids_rx_filtering[26] << 1), &regs->cantxfg[12].data[0]);
+	
+	flexcan_write(0x0, &regs->cantxfg[12].data[1]);
+	flexcan_write((can_ids_rx_filtering[27] << 1), &regs->cantxfg[12].data[1]);
+	
+	flexcan_write(0x0, &regs->cantxfg[13].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[28] << 1), &regs->cantxfg[13].can_ctrl);
+		
+	flexcan_write(0x0, &regs->cantxfg[13].can_id);
+	flexcan_write((can_ids_rx_filtering[29] << 1), &regs->cantxfg[13].can_id);
+
+	flexcan_write(0x0, &regs->cantxfg[13].data[0]);
+	flexcan_write((can_ids_rx_filtering[30] << 1), &regs->cantxfg[13].data[0]);
+	
+	flexcan_write(0x0, &regs->cantxfg[13].data[1]);
+	flexcan_write((can_ids_rx_filtering[31] << 1), &regs->cantxfg[13].data[1]);
+	
+	flexcan_write(0x0, &regs->cantxfg[14].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[32] << 1), &regs->cantxfg[14].can_ctrl);
+	
+	flexcan_write(0x0, &regs->cantxfg[14].can_id);
+	flexcan_write((can_ids_rx_filtering[33] << 1), &regs->cantxfg[14].can_id);
+	
+	flexcan_write(0x0, &regs->cantxfg[14].data[0]);
+	flexcan_write((can_ids_rx_filtering[34] << 1), &regs->cantxfg[14].data[0]);
+	
+	flexcan_write(0x0, &regs->cantxfg[14].data[1]);
+	flexcan_write((can_ids_rx_filtering[35] << 1), &regs->cantxfg[14].data[1]);
+	
+	flexcan_write(0x0, &regs->cantxfg[15].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[36] << 1), &regs->cantxfg[15].can_ctrl);
+		
+	flexcan_write(0x0, &regs->cantxfg[15].can_id);
+	flexcan_write((can_ids_rx_filtering[37] << 1), &regs->cantxfg[15].can_id);
+
+	flexcan_write(0x0, &regs->cantxfg[15].data[0]);
+	flexcan_write((can_ids_rx_filtering[38] << 1), &regs->cantxfg[15].data[0]);
+	
+	flexcan_write(0x0, &regs->cantxfg[15].data[1]);
+	flexcan_write((can_ids_rx_filtering[39] << 1), &regs->cantxfg[15].data[1]);
+
+	flexcan_write(0x0, &regs->cantxfg[16].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[40] << 1), &regs->cantxfg[16].can_ctrl);
+	
+	flexcan_write(0x0, &regs->cantxfg[16].can_id);
+	flexcan_write((can_ids_rx_filtering[41] << 1), &regs->cantxfg[16].can_id);
+
+	flexcan_write(0x0, &regs->cantxfg[16].data[0]);
+	flexcan_write((can_ids_rx_filtering[42] << 1), &regs->cantxfg[16].data[0]);
+	
+	flexcan_write(0x0, &regs->cantxfg[16].data[1]);
+	flexcan_write((can_ids_rx_filtering[43] << 1), &regs->cantxfg[16].data[1]);
+	
+	flexcan_write(0x0, &regs->cantxfg[17].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[44] << 1), &regs->cantxfg[17].can_ctrl);
+	
+	flexcan_write(0x0, &regs->cantxfg[17].can_id);
+	flexcan_write((can_ids_rx_filtering[45] << 1), &regs->cantxfg[17].can_id);
+	
+	flexcan_write(0x0, &regs->cantxfg[17].data[0]);
+	flexcan_write((can_ids_rx_filtering[46] << 1), &regs->cantxfg[17].data[0]);
+	
+	flexcan_write(0x0, &regs->cantxfg[17].data[1]);
+	flexcan_write((can_ids_rx_filtering[47] << 1), &regs->cantxfg[17].data[1]);
+	
+	flexcan_write(0x0, &regs->cantxfg[18].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[48] << 1), &regs->cantxfg[18].can_ctrl);
+		
+	flexcan_write(0x0, &regs->cantxfg[18].can_id);
+	flexcan_write((can_ids_rx_filtering[49] << 1), &regs->cantxfg[18].can_id);
+
+	flexcan_write(0x0, &regs->cantxfg[18].data[0]);
+	flexcan_write((can_ids_rx_filtering[50] << 1), &regs->cantxfg[18].data[0]);
+
+	flexcan_write(0x0, &regs->cantxfg[18].data[1]);
+	flexcan_write((can_ids_rx_filtering[51] << 1), &regs->cantxfg[18].data[1]);
+
+	flexcan_write(0x0, &regs->cantxfg[19].can_ctrl);
+	flexcan_write((can_ids_rx_filtering[52] << 1), &regs->cantxfg[19].can_ctrl);
+
+	/* acceptance mask/acceptance code (accept only matched ones) */
+	flexcan_write(0x01FFFE00, &regs->rxfgmask);
 
 	/*
 	 * On Vybrid, disable memory error detection interrupts
