#define __ASSEMBLY__ #include #include /*! Enable LPDDR4 derate workaround */ DEFINE LP4_MANUAL_DERATE_WORKAROUND /*! Configure DDR retention support */ DEFINE BD_DDR_RET /* Add/remove DDR retention */ DEFINE BD_DDR_RET_NUM_DRC 2 /* Number for DRCs to retain */ DEFINE BD_DDR_RET_NUM_REGION 6 /* DDR regions to save/restore */ /* Descriptor values for DDR regions saved/restored during retention */ DEFINE BD_DDR_RET_REGION1_ADDR 0x80000000 DEFINE BD_DDR_RET_REGION1_SIZE 64 DEFINE BD_DDR_RET_REGION2_ADDR 0x80008040 DEFINE BD_DDR_RET_REGION2_SIZE 16 DEFINE BD_DDR_RET_REGION3_ADDR 0x80010000 DEFINE BD_DDR_RET_REGION3_SIZE 48 DEFINE BD_DDR_RET_REGION4_ADDR 0x80001000 DEFINE BD_DDR_RET_REGION4_SIZE 64 DEFINE BD_DDR_RET_REGION5_ADDR 0x80009040 DEFINE BD_DDR_RET_REGION5_SIZE 16 DEFINE BD_DDR_RET_REGION6_ADDR 0x80011000 DEFINE BD_DDR_RET_REGION6_SIZE 48 /* * Device Configuration Data (DCD) Version 19 * * Each entry must have the format: * Addr-type Address Value * * where: * Addr-type register length (1,2 or 4 bytes) * Address absolute address of the register * value value to be stored in the register */ #ifndef SCFW_DCD /* For 1600MHz DDR, DRC 800MHz operation */ DATA 4 0xff148000 0x00000885 /* DRC0 bringup */ DATA 4 0xff1a0000 0x00000885 /* DRC1 bringup */ #else if (action != BOARD_DDR_COLD_INIT) { return SC_ERR_NONE; } #endif //------------------------------------------- // Reset controller core domain (required to configure it) //-------------------------------------------- DATA 4 0x41a40208 0x1 DATA 4 0x41d00208 0x1 DATA 4 0x41a40040 0xB DATA 4 0x41d00040 0xB DATA 4 0x41a40204 0x1 DATA 4 0x41d00204 0x1 //------------------------------------------- // Configure controller registers //-------------------------------------------- /* DRAM 0 controller configuration begin */ DATA 4 DDRC_MSTR_0 0xC3080020 // Set LPDDR4, BL = 16 and active ranks DATA 4 DDRC_DERATEEN_0 0x00000213 // derate enable, derate values, byte to read MRR data DATA 4 DDRC_DERATEINT_0 0x0186A000 // derate MR4 interval read DATA 4 DDRC_RFSHCTL0_0 0x0021F000 DATA 4 DDRC_RFSHTMG_0 0x00610090 // tREFI, tRFC DATA 4 DDRC_INIT0_0 0x4003061C // pre_cke = 2ms, post_cke = 2us DATA 4 DDRC_INIT1_0 0x009E0000 // dram_rstn = 200us DATA 4 DDRC_INIT3_0 0x0054002D // MR1, MR2 DATA 4 DDRC_INIT4_0 0x00F100C0 // MR3, MR13 DATA 4 DDRC_RANKCTL_0 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd DATA 4 DDRC_DRAMTMG0_0 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin DATA 4 DDRC_DRAMTMG1_0 0x00060633 // tXP, rd2pre, tRC DATA 4 DDRC_DRAMTMG2_0 0x07101617 // WL, RL, rd2wr, wr2rd DATA 4 DDRC_DRAMTMG3_0 0x00C0C000 // tmrw, tmrd, tmod DATA 4 DDRC_DRAMTMG4_0 0x0F04080F // trcd, tccd, trrd, trp DATA 4 DDRC_DRAMTMG5_0 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke DATA 4 DDRC_DRAMTMG6_0 0x02020007 // tckdpde, tckdpdx, tckcsx DATA 4 DDRC_DRAMTMG7_0 0x00000401 // tckpde, tckpdx DATA 4 DDRC_DRAMTMG12_0 0x00020610 // tCMDCKE, tCKEHCMD DATA 4 DDRC_DRAMTMG13_0 0x0C100002 // tODTLoff, tCCDMW, tPPD DATA 4 DDRC_DRAMTMG14_0 0x00000096 // txsr DATA 4 DDRC_ZQCTL0_0 0x03200018 // tZQCAL, tZQLAT DATA 4 DDRC_ZQCTL1_0 0x028061A8 // tZQReset, tzq_short_interval DATA 4 DDRC_DFITMG0_0 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat DATA 4 DDRC_DFITMG1_0 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable DATA 4 DDRC_DFITMG2_0 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat DATA 4 DDRC_DFIMISC_0 0x00000005 // dfi_data_cs_polarity DATA 4 DDRC_DFIUPD0_0 0x00400003 // Disable the automatic dfi_ctrlupd_req generation DATA 4 DDRC_DFIUPD1_0 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) DATA 4 DDRC_DFIUPD2_0 0x80000000 // dfi_phyupd_en DATA 4 DDRC_ADDRMAP0_0 0x00000007 // addrmap_cs_bit0 DATA 4 DDRC_ADDRMAP3_0 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 DATA 4 DDRC_ADDRMAP4_0 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated DATA 4 DDRC_ADDRMAP1_0 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 DATA 4 DDRC_ADDRMAP5_0 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 DATA 4 DDRC_ADDRMAP6_0 0x0F080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 DATA 4 DDRC_DBICTL_0 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 DATA 4 DDRC_ODTMAP_0 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt DATA 4 DDRC_PCTRL_0_0 0x00000001 // Enable port 0 /* DRAM 1 controller initialization */ DATA 4 DDRC_MSTR_1 0xC3080020 // Set LPDDR4, BL = 16 and active ranks DATA 4 DDRC_DERATEEN_1 0x00000223 // derate enable, derate values, byte to read MRR data DATA 4 DDRC_DERATEINT_1 0x0186A000 // derate MR4 interval read DATA 4 DDRC_RFSHCTL0_1 0x0021F000 DATA 4 DDRC_RFSHTMG_1 0x00610090 // tREFI, tRFC DATA 4 DDRC_INIT0_1 0x4003061C // pre_cke = 2ms, post_cke = 2us DATA 4 DDRC_INIT1_1 0x009E0000 // dram_rstn = 200us DATA 4 DDRC_INIT3_1 0x0054002D // MR1, MR2 DATA 4 DDRC_INIT4_1 0x00F100C0 // MR3, MR13 DATA 4 DDRC_RANKCTL_1 0x0000066F // diff_rank_wr_gap, diff_rank_rd_gap, max_rank_rd DATA 4 DDRC_DRAMTMG0_1 0x1A201B22 // wr2pr, tFAW, tRASmax, tRASmin DATA 4 DDRC_DRAMTMG1_1 0x00060633 // tXP, rd2pre, tRC DATA 4 DDRC_DRAMTMG2_1 0x07101617 // WL, RL, rd2wr, wr2rd DATA 4 DDRC_DRAMTMG3_1 0x00C0C000 // tmrw, tmrd, tmod DATA 4 DDRC_DRAMTMG4_1 0x0F04080F // trcd, tccd, trrd, trp DATA 4 DDRC_DRAMTMG5_1 0x02040C0C // tCKCKEH, tCKCKEL, tckesr, tcke DATA 4 DDRC_DRAMTMG6_1 0x02020007 // tckdpde, tckdpdx, tckcsx DATA 4 DDRC_DRAMTMG7_1 0x00000401 // tckpde, tckpdx DATA 4 DDRC_DRAMTMG12_1 0x00020610 // tCMDCKE, tCKEHCMD DATA 4 DDRC_DRAMTMG13_1 0x0C100002 // tODTLoff, tCCDMW, tPPD DATA 4 DDRC_DRAMTMG14_1 0x00000096 // txsr DATA 4 DDRC_ZQCTL0_1 0x03200018 // tZQCAL, tZQLAT DATA 4 DDRC_ZQCTL1_1 0x028061A8 // tZQReset, tzq_short_interval DATA 4 DDRC_DFITMG0_1 0x049E820C // dfi_t_ctrl_delay, dfi_t_rddata_en, dfi_tphy_wrdata, dfi_tphy_wrlat DATA 4 DDRC_DFITMG1_1 0x00070303 // dfi_t_wrdata_delay, dfi_t_dram_clk_disable, dfi_t_dram_clk_enable DATA 4 DDRC_DFITMG2_1 0x00001C0A // dfi_tphy_rdcslat, dfi_tphy_wrcslat DATA 4 DDRC_DFIMISC_1 0x00000005 // dfi_data_cs_polarity DATA 4 DDRC_DFIUPD0_1 0x00400003 // Disable the automatic dfi_ctrlupd_req generation DATA 4 DDRC_DFIUPD1_1 0x008000A0 // dfi_ctrlupd_req generation interval generation (min and max) DATA 4 DDRC_DFIUPD2_1 0x80000000 // dfi_phyupd_en DATA 4 DDRC_ADDRMAP0_1 0x00000007 // addrmap_cs_bit0 DATA 4 DDRC_ADDRMAP3_1 0x00000000 // addrmap_col_b9, addrmap_col_b8, addrmap_col_b7, addrmap_col_b6 DATA 4 DDRC_ADDRMAP4_1 0x00001F1F // addrmap_col_b10 and addrmap_col_b11 set to de-activated DATA 4 DDRC_ADDRMAP1_1 0x00080808 // addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 DATA 4 DDRC_ADDRMAP5_1 0x08080808 // addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 DATA 4 DDRC_ADDRMAP6_1 0x0F080808 // addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 DATA 4 DDRC_DBICTL_1 0x00000007 // rd_dbi_en=wr_dbi_en=dm_en=1 DATA 4 DDRC_ODTMAP_1 0x00000000 // rank[3:0]_wr_odt, rank[3:0]_wr_odt DATA 4 DDRC_PCTRL_0_1 0x00000001 // Enable port 0 //Performance optimizations DATA 4 DDRC_PWRCTL_0 0x0000010A DATA 4 DDRC_PWRCTL_1 0x0000010A DATA 4 DDRC_PWRTMG_0 0x00402010 DATA 4 DDRC_PWRTMG_1 0x00402010 DATA 4 DDRC_HWLPCTL_0 0x06FF0001 DATA 4 DDRC_HWLPCTL_1 0x06FF0001 //Enables DFI Low Power interface DATA 4 DDRC_DFILPCFG0_0 0x0700B100 DATA 4 DDRC_DFILPCFG0_1 0x0700B100 //------------------------------------------- // Release reset of controller core domain //-------------------------------------------- DATA 4 0x41a40208 0x1 DATA 4 0x41d00208 0x1 DATA 4 0x41a40040 0xF DATA 4 0x41d00040 0xF DATA 4 0x41a40204 0x1 DATA 4 0x41d00204 0x1 //------------------------------------------- // Configure PHY registers for PHY initialization //-------------------------------------------- /* DRAM 0 controller configuration begin */ // Set-up DRAM Configuration Register DATA 4 DDR_PHY_DCR_0 0x0000040D // LPDDR4 selection with 8 bank // Set-up byte and bit swapping registers DATA 4 DDR_PHY_PGCR8_0 0x000F0009 DATA 4 DDR_PHY_DX0DQMAP0_0 0x00003465 // DQ bit 0/1/2/3/4 remapping DATA 4 DDR_PHY_DX0DQMAP1_0 0x00008271 // DQ bit 5/6/7 and DM remapping DATA 4 DDR_PHY_DX1DQMAP0_0 0x00075632 // DQ bit 0/1/2/3/4 remapping DATA 4 DDR_PHY_DX1DQMAP1_0 0x00008104 // DQ bit 5/6/7 and DM remapping DATA 4 DDR_PHY_DX2DQMAP0_0 0x00064732 // DQ bit 0/1/2/3/4 remapping DATA 4 DDR_PHY_DX2DQMAP1_0 0x00008015 // DQ bit 5/6/7 and DM remapping DATA 4 DDR_PHY_DX3DQMAP0_0 0x00012574 // DQ bit 0/1/2/3/4 remapping DATA 4 DDR_PHY_DX3DQMAP1_0 0x00008360 // DQ bit 5/6/7 and DM remapping DATA 4 DDR_PHY_CATR0_0 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY DATA 4 DDR_PHY_CATR1_0 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY // Set-up PHY General Configuration Register SET_BIT 4 DDR_PHY_PGCR1_0 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 DATA 4 DDR_PHY_PGCR0_0 0x87001E00 // Set ADCP=1 (Address Copy) DATA 4 DDR_PHY_PGCR2_0 0x00F0D879 // Set tREFPRD DATA 4 DDR_PHY_PGCR3_0 0x050A1080 // CKEN/CKNEN toggling and polarity // Set-up PHY Timing Register DATA 4 DDR_PHY_PTR0_0 0x64032010 // tPLLPD, tPLLGS, tPHYRST DATA 4 DDR_PHY_PTR1_0 0x4E201C20 // tPLLLOCK, tPLLRST // Set-up PLL Control Register DATA 4 DDR_PHY_PLLCR0_0 0x801C0000 DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0x801C0000 // Set-up Impedance Control Register DATA 4 DDR_PHY_ZQCR_0 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) // ZPROG_DRAM_ODT and ZPROG_HOST_ODT DATA 4 DDR_PHY_ZQ0PR0_0 0x0001B9BB // Impedance control for CA bus DATA 4 DDR_PHY_ZQ1PR0_0 0x0001B9BB // Impedance control for DQ bus // Set-up PHY Initialization Register /* DRAM 1 controller configuration begin */ // Set-up DRAM Configuration Register DATA 4 DDR_PHY_DCR_1 0x0000040D // LPDDR4 selection with 8 bank // Set-up byte and bit swapping registers DATA 4 DDR_PHY_PGCR8_1 0x000F0009 DATA 4 DDR_PHY_DX0DQMAP0_1 0x00003465 // DQ bit 0/1/2/3/4 remapping DATA 4 DDR_PHY_DX0DQMAP1_1 0x00008271 // DQ bit 5/6/7 and DM remapping DATA 4 DDR_PHY_DX1DQMAP0_1 0x00075632 // DQ bit 0/1/2/3/4 remapping DATA 4 DDR_PHY_DX1DQMAP1_1 0x00008104 // DQ bit 5/6/7 and DM remapping DATA 4 DDR_PHY_DX2DQMAP0_1 0x00064732 // DQ bit 0/1/2/3/4 remapping DATA 4 DDR_PHY_DX2DQMAP1_1 0x00008015 // DQ bit 5/6/7 and DM remapping DATA 4 DDR_PHY_DX3DQMAP0_1 0x00012574 // DQ bit 0/1/2/3/4 remapping DATA 4 DDR_PHY_DX3DQMAP1_1 0x00008360 // DQ bit 5/6/7 and DM remapping DATA 4 DDR_PHY_CATR0_1 0x00141032 // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY DATA 4 DDR_PHY_CATR1_1 0x0013AAAA // Only for LPDDR3 but used here to know how LPDDR4 bytes are connected to PHY // Set-up PHY General Configuration Register SET_BIT 4 DDR_PHY_PGCR1_1 0x000A0040 // DISDIC=1 (no uMCTL2 commands can go to memory), WDQSEXT=1, PUBMODE=1 DATA 4 DDR_PHY_PGCR0_1 0x87001E00 // Set ADCP=1 (Address Copy) DATA 4 DDR_PHY_PGCR2_1 0x00F0D879 // Set tREFPRD DATA 4 DDR_PHY_PGCR3_1 0x050A1080 // CKEN/CKNEN toggling and polarity // Set-up PHY Timing Register DATA 4 DDR_PHY_PTR0_1 0x64032010 // tPLLPD, tPLLGS, tPHYRST DATA 4 DDR_PHY_PTR1_1 0x4E201C20 // tPLLLOCK, tPLLRST // Set-up PLL Control Register DATA 4 DDR_PHY_PLLCR0_1 0x801C0000 DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0x801C0000 // Set-up Impedance Control Register DATA 4 DDR_PHY_ZQCR_1 0x008C2C58 // Set ODT_MODE=0b10(LPDDR4 stype pullup) // ZPROG_DRAM_ODT and ZPROG_HOST_ODT DATA 4 DDR_PHY_ZQ0PR0_1 0x0001B9BB // Impedance control for CA bus DATA 4 DDR_PHY_ZQ1PR0_1 0x0001B9BB // Impedance control for DQ bus //------------------------------------------- // Launch PLL init //-------------------------------------------- DATA 4 DDR_PHY_PIR_0 0x10 DATA 4 DDR_PHY_PIR_0 0x11 DATA 4 DDR_PHY_PIR_1 0x10 DATA 4 DDR_PHY_PIR_1 0x11 // Wait end of PLL init (Wait for bit 0 of PGSR0 to be '1') CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 //------------------------------------------- // Switch to boot frequency and launch DCAL+ZCAL //-------------------------------------------- /* DRAM 0 */ DATA 4 DDR_PHY_PLLCR0_0 0xA01C0000 // Put PLL in power down state DATA 4 DDR_PHY_DX8SLbPLLCR0_0 0xA01C0000 // Switch to boot frequency DATA 4 0x41a40208 0x1 // Gate functional clock to avoid glitches DATA 4 0x41a40504 0x00800000 // Set bypass mode in DSC GPR control register DATA 4 0x41a40204 0x1 // Ungate functional clock // Set PLL timings for boot frequency DATA 4 DDR_PHY_PTR0_0 0x03201901 DATA 4 DDR_PHY_PTR1_0 0x027100E1 // Launch DCAL+ZCAL DATA 4 DDR_PHY_PIR_0 0x22 DATA 4 DDR_PHY_PIR_0 0x23 /* DRAM 1 */ DATA 4 DDR_PHY_PLLCR0_1 0xA01C0000 // Put PLL in power down state DATA 4 DDR_PHY_DX8SLbPLLCR0_1 0xA01C0000 // Switch to boot frequency DATA 4 0x41d00208 0x1 DATA 4 0x41d00504 0x00800000 DATA 4 0x41d00204 0x1 // Set PLL timings for boot frequency DATA 4 DDR_PHY_PTR0_1 0x03201901 DATA 4 DDR_PHY_PTR1_1 0x027100E1 // Launch DCAL+ZCAL DATA 4 DDR_PHY_PIR_1 0x22 DATA 4 DDR_PHY_PIR_1 0x23 //------------------------------------------- // Configure registers for DRAM initialization //------------------------------------------- /* DRAM 0 */ // Set-up Mode Register // MR0, MR3, MR4, MR5 MR6 are untouched DATA 4 DDR_PHY_MR1_0 0x54 // Set BL, WR-PRE, nWR, RPST DATA 4 DDR_PHY_MR2_0 0x2D // Set RL/WL DATA 4 DDR_PHY_MR3_0 0xF1 // Set drive strength DATA 4 DDR_PHY_MR11_0 0x54 // Set CA ODT and DQ ODT DATA 4 DDR_PHY_MR13_0 0xC0 DATA 4 DDR_PHY_MR22_0 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) /* LPDDR4 mode register writes for CA and DQ VREF settings */ DATA 4 DDR_PHY_MR12_0 0x48 DATA 4 DDR_PHY_MR14_0 0x48 // Set-up DRAM Timing Parameters Register // DTPR6 is untouched DATA 4 DDR_PHY_DTPR0_0 0x1044220C // tRRD, tRAS, tRP, tRTP DATA 4 DDR_PHY_DTPR1_0 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD DATA 4 DDR_PHY_DTPR2_0 0x006CA12C // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS DATA 4 DDR_PHY_DTPR3_0 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK DATA 4 DDR_PHY_DTPR4_0 0x01202B0F // tRFC, tWLO, tXP DATA 4 DDR_PHY_DTPR5_0 0x21651D11 // tRC, tRCD, tWTR // Set-up PHY Timing Register DATA 4 DDR_PHY_PTR2_0 0x000A3DEF // tWLDLYS DATA 4 DDR_PHY_PTR3_0 0x000186A0 // tDINIT0 DATA 4 DDR_PHY_PTR4_0 0x00000064 // tDINIT1 DATA 4 DDR_PHY_PTR5_0 0x00002710 // tDINIT2 DATA 4 DDR_PHY_PTR6_0 0x00B00032 // tDINIT4, tDINIT3 // Set-up ODT Configuration Register // DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. DATA 4 DDR_PHY_RANKIDR_0 0x00000001 // Select rank 1 to write DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank1 disabled DATA 4 DDR_PHY_RANKIDR_0 0x00000000 // Select rank 0 to write DATA 4 DDR_PHY_ODTCR_0 0x00000000 // ODT of rank0 disabled // Set-up AC I/O Configuration Register // ACIOCR1-4 are untouched DATA 4 DDR_PHY_ACIOCR0_0 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 DATA 4 DDR_PHY_ACIOCR5_0 0x09000000 // I/O mode = LPDDR4 // Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. DATA 4 DDR_PHY_ACIOCR1_0 0x44000000 // Set-up VREF Training Control Registers DATA 4 DDR_PHY_VTCR0_0 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 DATA 4 DDR_PHY_VTCR1_0 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 // Set-up DATX8 General Configuration Registers // DXnGCR0-4 are untouched SET_BIT 4 DDR_PHY_PGCR5_0 0x4 DATA 4 DDR_PHY_PGCR6_0 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit // Set-up DATX8 General Configuration Registers DATA 4 DDR_PHY_DX0GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults DATA 4 DDR_PHY_DX1GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults DATA 4 DDR_PHY_DX2GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults DATA 4 DDR_PHY_DX3GCR5_0 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults DATA 4 DDR_PHY_DX0GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults DATA 4 DDR_PHY_DX1GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults DATA 4 DDR_PHY_DX2GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults DATA 4 DDR_PHY_DX3GCR4_0 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults // Set-up DATX8 DX Control Register 2 // PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH DATA 4 DDR_PHY_DX8SLbDXCTL2_0 0x001C1600 DATA 4 DDR_PHY_PGCR4_0 0x001900B1 // Set-up DATX8 IO Control Register DATA 4 DDR_PHY_DX8SLbIOCR_0 0x79000000 // I/O mode = LPDDR4 /* DRAM 1 */ // Set-up Mode Register // MR0, MR3, MR4, MR5 MR6 are untouched DATA 4 DDR_PHY_MR1_1 0x54 // Set BL, WR-PRE, nWR, RPST DATA 4 DDR_PHY_MR2_1 0x2D // Set RL/WL DATA 4 DDR_PHY_MR3_1 0xF1 // Set drive strength DATA 4 DDR_PHY_MR11_1 0x54 // Set CA ODT and DQ ODT DATA 4 DDR_PHY_MR13_1 0xC0 DATA 4 DDR_PHY_MR22_1 0x16 // Set ODTE-CS=1 (overrides ODT_CA for CS1 as CS not shared between ranks) /* LPDDR4 mode register writes for CA and DQ VREF settings */ DATA 4 DDR_PHY_MR12_1 0x48 DATA 4 DDR_PHY_MR14_1 0x48 // Set-up DRAM Timing Parameters Register // DTPR6 is untouched DATA 4 DDR_PHY_DTPR0_1 0x1044220C // tRRD, tRAS, tRP, tRTP DATA 4 DDR_PHY_DTPR1_1 0x28400417 // tWLMRD, tFAW, tODTUP, tMRD DATA 4 DDR_PHY_DTPR2_1 0x006CA12C // tRTW, tRTODT, tCMDCKE, tCKE, tVRCG, tXS DATA 4 DDR_PHY_DTPR3_1 0x01800602 // tODX, tCCD, tDLLK, tDQSCKmax, tDQSCK DATA 4 DDR_PHY_DTPR4_1 0x01202B0F // tRFC, tWLO, tXP DATA 4 DDR_PHY_DTPR5_1 0x21651D11 // tRC, tRCD, tWTR // Set-up PHY Timing Register DATA 4 DDR_PHY_PTR2_1 0x000A3DEF DATA 4 DDR_PHY_PTR3_1 0x000186A0 // tDINIT0 DATA 4 DDR_PHY_PTR4_1 0x00000064 // tDINIT1 DATA 4 DDR_PHY_PTR5_1 0x00002710 // tDINIT2 DATA 4 DDR_PHY_PTR6_1 0x00B00032 // tDINIT4, tDINIT3 (1us) // Set-up ODT Configuration Register // DDR ODT_CA signal is tied at boundary of DDR. Thus no need to drive it dynamically. DATA 4 DDR_PHY_RANKIDR_1 0x00000001 // Select rank 1 to write DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank1 disabled DATA 4 DDR_PHY_RANKIDR_1 0x00000000 // Select rank 0 to write DATA 4 DDR_PHY_ODTCR_1 0x00000000 // ODT of rank0 disabled // Set-up AC I/O Configuration Register // ACIOCR1-4 are untouched DATA 4 DDR_PHY_ACIOCR0_1 0x30070801 // PNUM2 (i.e.LPDDR4) selection [10:11] = 0x2 DATA 4 DDR_PHY_ACIOCR5_1 0x09000000 // I/O mode = LPDDR4 // Due to address copy set A[13] (=cke_B[0]) and A[15] (=cke_B[1]) outputs as always ON. DATA 4 DDR_PHY_ACIOCR1_1 0x44000000 // Set-up VREF Training Control Registers DATA 4 DDR_PHY_VTCR0_1 0xF0032008 // CK1, CK0, DRAM VREF set to same as MR12 DATA 4 DDR_PHY_VTCR1_1 0x07F001AF // HVIO=1, SHREN=1, SHRNK=0 // Set-up DATX8 General Configuration Registers // DXnGCR0-4 are untouched SET_BIT 4 DDR_PHY_PGCR5_1 0x4 DATA 4 DDR_PHY_PGCR6_1 0x00033200 // Enable CSN Bit Delay VT Compensation (AC already enabled by default) + drift limit // Set-up DATX8 General Configuration Registers DATA 4 DDR_PHY_DX0GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults DATA 4 DDR_PHY_DX1GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults DATA 4 DDR_PHY_DX2GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults DATA 4 DDR_PHY_DX3GCR5_1 0x09092020 // Set DXREFISELR0 and DXREFISELR1 to 0x30, maintain other defaults DATA 4 DDR_PHY_DX0GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults DATA 4 DDR_PHY_DX1GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults DATA 4 DDR_PHY_DX2GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults DATA 4 DDR_PHY_DX3GCR4_1 0x0E00BF3C // Set DXREFSSEL,DXREFSSELRANGE,DXREFSEN,DXREFIEN, maintain other defaults // Set-up DATX8 DX Control Register 2 // PREOEX=2.5tCK (0.5 more than MR1), POSOEX=1tCK (0.5 more than in MR3), LPWAKEUP_THRSH DATA 4 DDR_PHY_DX8SLbDXCTL2_1 0x001C1600 DATA 4 DDR_PHY_PGCR4_1 0x001900B1 // Set-up DATX8 IO Control Register DATA 4 DDR_PHY_DX8SLbIOCR_1 0x79000000 // I/O mode = LPDDR4 //------------------------------------------- // Wait end of PHY initialization then launch DRAM initialization //------------------------------------------- /* DRAM 0 */ // Wait for bit 0 of PGSR0 to be '1' CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 // Launch DRAM initialization (set bit 0) DATA 4 DDR_PHY_PIR_0 0x180 DATA 4 DDR_PHY_PIR_0 0x181 /* DRAM 1 */ // Wait for bit 0 of PGSR0 to be '1' CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 // Launch DRAM initialization (set bit 0) DATA 4 DDR_PHY_PIR_1 0x180 DATA 4 DDR_PHY_PIR_1 0x181 //------------------------------------------- // Wait end of DRAM initialization then launch second DRAM initialization // This is required due to errata e10945: // Title: "PUB does not program LPDDR4 DRAM MR22 prior to running DRAM ZQ calibration" // Workaround: "Run DRAM Initialization twice" //------------------------------------------- /* DRAM 0 */ // Wait for bit 0 of PGSR0 to be '1' CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 // tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. DATA 4 DDR_PHY_PTR3_0 0x00000064 // Launch DRAM initialization (set bit 0) DATA 4 DDR_PHY_PIR_0 0x100 DATA 4 DDR_PHY_PIR_0 0x101 /* DRAM 1 */ // Wait for bit 0 of PGSR0 to be '1' CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 // tDINIT0 reduced to 2us instead of 2ms. No need to wait the 2ms for the second DRAM init. DATA 4 DDR_PHY_PTR3_1 0x00000064 // Launch DRAM initialization (set bit 0) DATA 4 DDR_PHY_PIR_1 0x100 DATA 4 DDR_PHY_PIR_1 0x101 //------------------------------------------- // Wait end of second DRAM initialization //------------------------------------------- // DRAM 0 initialization end CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 // DRAM 1 initialization end CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 //------------------------------------------- // Run CBT (Command Bus Training) //------------------------------------------- //Call run_cbt(initial DDR_PHY_PTR0 value, initial DDR_PHY_PTR1 value, total_num_drc) here run_cbt(0x64032010, 0x4E201C20, 2); //---------------------------------------------------------------// // DATA training //---------------------------------------------------------------// // configure PHY for data training // The following register writes are recommended by SNPS prior to running training CLR_BIT 4 DDR_PHY_DQSDR0_0 0x00000001 // Disable drift SET_BIT 4 DDR_PHY_PGCR6_0 0x00000001 // Disable VT compensation CHECK_BITS_SET 4 DDR_PHY_PGSR1_0 0x40000000 // Disable VT compensation SET_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=1; PUBMODE=1 // Per SNPS initialize BIST registers for VREF training DATA 4 DDR_PHY_BISTAR1_0 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) DATA 4 DDR_PHY_BISTAR2_0 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) DATA 4 DDR_PHY_BISTAR4_0 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) CLR_BIT 4 DDR_PHY_DQSDR0_1 0x00000001 // Disable drift SET_BIT 4 DDR_PHY_PGCR6_1 0x00000001 // Disable VT compensation CHECK_BITS_SET 4 DDR_PHY_PGSR1_1 0x40000000 // Disable VT compensation SET_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=1; PUBMODE=1 // Per SNPS initialize BIST registers for VREF training DATA 4 DDR_PHY_BISTAR1_1 0x00010100 //BMRANK=1 (maximum rank minus 1); BIST Address Increment: 0x10 (16) DATA 4 DDR_PHY_BISTAR2_1 0x700003FF // BMBANK=8; BMCOL=0x400 (limit to min cols in JEDEC) DATA 4 DDR_PHY_BISTAR4_1 0x00003FFF // BMROW=0x4000 (limit to min rows in JEDEC) // Set-up Data Training Configuration Register // Note that DTCR0.RFSHDT are set to 0x0 as a workaround for errata e10946 (Synopsys // case 9001045655: Design limitation in LPDDR4 mode: REFRESH must be disabled during DQS2DQ training). DATA 4 DDR_PHY_DTCR0_0 0x000071C7 // Set DTRPTN to 0x7. RFSHDT=0 DATA 4 DDR_PHY_DTCR1_0 0x00030236 // Set RANKEN DATA 4 DDR_PHY_DTCR0_1 0x000071C7 // Set DTRPTN to 0x7. RFSHDT=0 DATA 4 DDR_PHY_DTCR1_1 0x00030236 // Set RANKEN // Launch Write leveling DATA 4 DDR_PHY_PIR_0 0x200 DATA 4 DDR_PHY_PIR_0 0x201 DATA 4 DDR_PHY_PIR_1 0x200 DATA 4 DDR_PHY_PIR_1 0x201 // Wait Write leveling to complete CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00200000 // Set DQS/DQSn glitch suppression resistor for training PHY0 to satisfy errata e10947 DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x012240B3 // Launch Read DQS training DATA 4 DDR_PHY_PIR_0 0x400 DATA 4 DDR_PHY_PIR_0 0x401 // Wait Write leveling to complete CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00200000 // Set DQS/DQSn glitch suppression resistor for training PHY1 to satisfy errata e10947 DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x012240B3 // Launch Read DQS training DATA 4 DDR_PHY_PIR_1 0x400 DATA 4 DDR_PHY_PIR_1 0x401 // Wait Read DQS training to complete PHY0 CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00400000 // Remove DQS/DQSn glitch suppression resistor PHY0 DATA 4 DDR_PHY_DX8SLbDQSCTL_0 0x01224000 // DQS2DQ training, Write leveling, Deskew and eye trainings DATA 4 DDR_PHY_PIR_0 0x0010F800 DATA 4 DDR_PHY_PIR_0 0x0010F801 // Wait Read DQS training to complete PHY1 CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00400000 // Remove DQS/DQSn glitch suppression resistor PHY1 DATA 4 DDR_PHY_DX8SLbDQSCTL_1 0x01224000 // DQS2DQ training, Write leveling, Deskew and eye trainings DATA 4 DDR_PHY_PIR_1 0x0010F800 DATA 4 DDR_PHY_PIR_1 0x0010F801 // Wait for training to complete CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x7FF40000 CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x7FF40000 // Launch VREF training DATA 4 DDR_PHY_PIR_0 0x00020000 DATA 4 DDR_PHY_PIR_0 0x00020001 DATA 4 DDR_PHY_PIR_1 0x00020000 DATA 4 DDR_PHY_PIR_1 0x00020001 // Wait for training to complete CHECK_BITS_SET 4 DDR_PHY_PGSR0_0 0x1 CHECK_BITS_CLR 4 DDR_PHY_PGSR0_0 0x00080000 CHECK_BITS_SET 4 DDR_PHY_PGSR0_1 0x1 CHECK_BITS_CLR 4 DDR_PHY_PGSR0_1 0x00080000 DATA 4 DDR_PHY_DX8SLbDDLCTL_0 0x00100002 DATA 4 DDR_PHY_DX8SLbDDLCTL_1 0x00100002 //Re-allow uMCTL2 to send commands to DDR CLR_BIT 4 DDR_PHY_PGCR1_0 0x00020040 // DISDIC=0, PUBMODE=0 CLR_BIT 4 DDR_PHY_PGCR1_1 0x00020040 // DISDIC=0, PUBMODE=0 //DQS Drift Registers PHY0 CLR_BIT 4 DDR_PHY_DX0GCR3_0 0x08000000 CLR_BIT 4 DDR_PHY_DX1GCR3_0 0x08000000 CLR_BIT 4 DDR_PHY_DX2GCR3_0 0x08000000 CLR_BIT 4 DDR_PHY_DX3GCR3_0 0x08000000 // Enable DQS drift detection PHY0 DATA 4 DDR_PHY_DQSDR0_0 0x20188005 DATA 4 DDR_PHY_DQSDR1_0 0xA8AA0000 DATA 4 DDR_PHY_DQSDR2_0 0x00070200 //DQS Drift Registers PHY1 CLR_BIT 4 DDR_PHY_DX0GCR3_1 0x08000000 CLR_BIT 4 DDR_PHY_DX1GCR3_1 0x08000000 CLR_BIT 4 DDR_PHY_DX2GCR3_1 0x08000000 CLR_BIT 4 DDR_PHY_DX3GCR3_1 0x08000000 // Enable DQS drift detection PHY1 DATA 4 DDR_PHY_DQSDR0_1 0x20188005 DATA 4 DDR_PHY_DQSDR1_1 0xA8AA0000 DATA 4 DDR_PHY_DQSDR2_1 0x00070200 //Enable QCHAN HWidle DATA 4 0x41A40504 0x400 DATA 4 0x41D00504 0x400 // Enable VT compensation CLR_BIT 4 DDR_PHY_PGCR6_0 0x1 CLR_BIT 4 DDR_PHY_PGCR6_1 0x1 //Check that controller is ready to operate CHECK_BITS_SET 4 DDRC_STAT_0 0x1 CHECK_BITS_SET 4 DDRC_STAT_1 0x1 ddrc_lpddr4_derate_init(BD_DDR_RET_NUM_DRC);