pinctrl_pcie1: pcie1grp {
                fsl,pins = <
                        MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29               0x16 /* open drain, pull up */
                        MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19               0x16 /* PCIE2_RESETn */
                        MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10               0x16 /* PCIE2_WAKE */
                        MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15               0x16 /* SSD_PWR_EN */
                >;
        };



&pcie1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pcie1>;
        reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
        clkreq-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>;
        clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
                 <&clk IMX8MQ_CLK_PCIE2_AUX>,
                 <&clk IMX8MQ_CLK_PCIE2_PHY>,
                 <&pcie1_refclk>;
        clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
        reserved-region = <&rpmsg_reserved>;
        ext_osc = <1>;
        status = "okay";
};