Initializing....using SPD 6 GiB left unmapped Loading second stage boot loader ................................................................................................. U-Boot 2016.01 (Feb 20 2024 - 09:55:28 +0530) CPU0: T1022, Version: 1.1, (0x85210211) Core: e5500, Version: 2.1, (0x80241021) Single Source Clock Configuration Clock Configuration: CPU0:1400 MHz, CPU1:1400 MHz, CCB:600 MHz, DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:150 MHz QE:300 MHz FMAN1: 600 MHz QMAN: 300 MHz PME: 300 MHz L1: D-cache 32 KiB enabled I-cache 32 KiB enabled Reset Configuration Word (RCW): 00000000: 0c10000e 0e000000 00000000 00000000 00000010: 85000000 00400012 ec110000 21000000 00000020: 00000000 00000000 60000000 00039000 00000030: 00000000 d416aa05 00000000 00000000 I2C: ready Board: T1022 SPI: ready DRAM: Detected UDIMM 78.C1GST.4030B 8 GiB (DDR4, 64-bit, CL=11, ECC on) L2: 256 KiB enabled Corenet Platform Cache: 256 KiB enabled Using SERDES1 Protocol: 133 (0x85) NAND: 8192 MiB MMC: FSL_SDHC: 0 SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB PCIe1: Root Complex, x1 gen2, regs @ 0xfe240000 01:00.0 - 14e4:8470 - Network controller 01:00.1 - 14e4:8470 - Network controller PCIe1: Bus 00 - 01 PCIe2: Root Complex, no link, regs @ 0xfe250000 PCIe2: Bus 02 - 02 PCIe3: disabled PCIe4: disabled In: serial Out: serial Err: serial SERDES Reference : 0x85 Net: Initializing Fman SF: Detected N25Q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB Fman1: Uploading microcode version 106.4.18 Could not get PHY for FSL_MDIO0: addr 0 Failed to connect Could not get PHY for FSL_MDIO0: addr 0 Failed to connect Could not get PHY for FSL_MDIO0: addr 0 Failed to connect Could not get PHY for FSL_MDIO0: addr 0 Failed to connect FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3 [PRIME], FM1@DTSEC4, FM1@DTSEC5 Hit any key to stop autoboot: 0 => mtest 0x10000000 0x20000000 Testing 10000000 ... 20000000: Iteration: 842