--- rel_imx_5.4.70_2.3.0/imx-atf/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c	2021-01-20 09:43:53.000000000 +0800
+++ rel_imx_5.4.70_2.3.0_uart4/imx-atf/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c	2021-03-11 10:29:54.108931338 +0800
@@ -58,7 +58,7 @@
 	RDC_MDAn(RDC_MDA_M4, DID1),
 
 	/* peripherals domain permission */
-	RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W),
+	RDC_PDAPn(RDC_PDAP_UART4, D0R | D0W),
 	RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
 
 	/* memory region */

--- rel_imx_5.4.70_2.3.0/imx-atf/plat/imx/imx8m/imx8mm/include/platform_def.h	2021-01-20 09:43:53.000000000 +0800
+++ rel_imx_5.4.70_2.3.0_uart4/imx-atf/plat/imx/imx8m/imx8mm/include/platform_def.h	2021-03-10 16:57:07.299870347 +0800
@@ -51,7 +51,7 @@
 
 #define HAB_RVT_BASE			U(0x00000900) /* HAB_RVT for i.MX8MM */
 
-#define IMX_BOOT_UART_BASE		U(0x30890000)
+#define IMX_BOOT_UART_BASE		U(0x30a60000)
 #define IMX_BOOT_UART_CLK_IN_HZ		24000000 /* Select 24MHz oscillator */
 
 #define PLAT_CRASH_UART_BASE		IMX_BOOT_UART_BASE

diff -Nuar rel_imx_5.4.70_2.3.0/uboot-imx/arch/arm/dts/imx8mm-evk.dts rel_imx_5.4.70_2.3.0_uart4/uboot-imx/arch/arm/dts/imx8mm-evk.dts
--- rel_imx_5.4.70_2.3.0/uboot-imx/arch/arm/dts/imx8mm-evk.dts	2021-01-20 09:40:04.000000000 +0800
+++ rel_imx_5.4.70_2.3.0_uart4/uboot-imx/arch/arm/dts/imx8mm-evk.dts	2021-03-11 11:08:06.495346395 +0800
@@ -13,8 +13,8 @@
 	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
 
 	chosen {
-		bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
-		stdout-path = &uart2;
+		bootargs = "console=ttymxc3,115200 earlycon=ec_imx6q,0x30a60000,115200";
+		stdout-path = &uart4;
 	};
 
 	leds {
@@ -360,9 +360,9 @@
 	status = "okay";
 };
 
-&uart2 { /* console */
+&uart4 { /* console */
 	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart2>;
+	pinctrl-0 = <&pinctrl_uart4>;
 	status = "okay";
 };
 
@@ -545,10 +545,10 @@
 		>;
 	};
 
-	pinctrl_uart2: uart2grp {
+	pinctrl_uart4: uart4grp {
 		fsl,pins = <
-			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
-			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
 		>;
 	};
 
diff -Nuar rel_imx_5.4.70_2.3.0/uboot-imx/arch/arm/dts/imx8mm-evk-u-boot.dtsi rel_imx_5.4.70_2.3.0_uart4/uboot-imx/arch/arm/dts/imx8mm-evk-u-boot.dtsi
--- rel_imx_5.4.70_2.3.0/uboot-imx/arch/arm/dts/imx8mm-evk-u-boot.dtsi	2021-01-20 09:40:04.000000000 +0800
+++ rel_imx_5.4.70_2.3.0_uart4/uboot-imx/arch/arm/dts/imx8mm-evk-u-boot.dtsi	2021-03-11 11:07:30.791183967 +0800
@@ -75,7 +75,7 @@
 	u-boot,dm-spl;
 };
 
-&pinctrl_uart2 {
+&pinctrl_uart4 {
 	u-boot,dm-spl;
 };
 
@@ -112,6 +112,13 @@
 };
 
 &uart2 {
+        dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
+        dma-names = "rx", "tx";
+};
+
+&uart4 {
+        /delete-property/ dmas;
+        /delete-property/ dmas-names;
 	u-boot,dm-spl;
 };
 
diff -Nuar rel_imx_5.4.70_2.3.0/uboot-imx/board/freescale/imx8mm_evk/imx8mm_evk.c rel_imx_5.4.70_2.3.0_uart4/uboot-imx/board/freescale/imx8mm_evk/imx8mm_evk.c
--- rel_imx_5.4.70_2.3.0/uboot-imx/board/freescale/imx8mm_evk/imx8mm_evk.c	2021-01-20 09:40:07.000000000 +0800
+++ rel_imx_5.4.70_2.3.0_uart4/uboot-imx/board/freescale/imx8mm_evk/imx8mm_evk.c	2021-03-10 17:34:51.283838262 +0800
@@ -23,8 +23,8 @@
 #define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
 
 static iomux_v3_cfg_t const uart_pads[] = {
-	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART4_RXD_UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART4_TXD_UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 
 static iomux_v3_cfg_t const wdog_pads[] = {
@@ -75,7 +75,7 @@
 
 	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 
-	init_uart_clk(1);
+	init_uart_clk(3);
 
 #ifdef CONFIG_NAND_MXS
 	setup_gpmi_nand(); /* SPL will call the board_early_init_f */

diff -Nuar rel_imx_5.4.70_2.3.0/uboot-imx/include/configs/imx8mm_evk.h rel_imx_5.4.70_2.3.0_uart4/uboot-imx/include/configs/imx8mm_evk.h
--- rel_imx_5.4.70_2.3.0/uboot-imx/include/configs/imx8mm_evk.h	2021-01-20 09:40:12.000000000 +0800
+++ rel_imx_5.4.70_2.3.0_uart4/uboot-imx/include/configs/imx8mm_evk.h	2021-03-11 10:00:37.909507016 +0800
@@ -106,8 +106,8 @@
 	"fdt_addr=0x43000000\0"			\
 	"fdt_high=0xffffffffffffffff\0" \
 	"mtdparts=" MFG_NAND_PARTITION "\0" \
-	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
-	"bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs "  \
+	"console=ttymxc3,115200 earlycon=ec_imx6q,0x30a60000,115200\0" \
+	"bootargs=console=ttymxc3,115200 earlycon=ec_imx6q,0x30a60000,115200 ubi.mtd=nandrootfs "  \
 		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
 		MFG_NAND_PARTITION \
 		"\0" \
@@ -122,7 +122,7 @@
 	"script=boot.scr\0" \
 	"image=Image\0" \
 	"splashimage=0x50000000\0" \
-	"console=ttymxc1,115200\0" \
+	"console=ttymxc3,115200\0" \
 	"fdt_addr=0x43000000\0"			\
 	"fdt_high=0xffffffffffffffff\0"		\
 	"boot_fit=no\0" \
@@ -216,7 +216,7 @@
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
 
-#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+#define CONFIG_MXC_UART_BASE		UART4_BASE_ADDR
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "

diff -Nuar rel_imx_5.4.70_2.3.0/linux-imx/arch/arm64/boot/dts/freescale/imx8mm-evk.dts rel_imx_5.4.70_2.3.0_uart4/linux-imx/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
--- rel_imx_5.4.70_2.3.0/linux-imx/arch/arm64/boot/dts/freescale/imx8mm-evk.dts	2021-01-20 09:41:16.000000000 +0800
+++ rel_imx_5.4.70_2.3.0_uart4/linux-imx/arch/arm64/boot/dts/freescale/imx8mm-evk.dts	2021-03-11 11:45:25.966948266 +0800
@@ -24,7 +24,7 @@
 	};
 
 	chosen {
-		stdout-path = &uart2;
+		stdout-path = &uart4;
 	};
 
 	leds {
@@ -344,9 +344,19 @@
 	status = "okay";
 };
 
-&uart2 { /* console */
+&uart2 { 
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart2>;
+	dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
+	dma-names = "rx", "tx";
+	status = "okay";
+};
+
+&uart4 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	/delete-property/ dmas;
+	/delete-property/ dmas-names;
 	status = "okay";
 };
 
@@ -902,6 +912,13 @@
 		>;
 	};
 
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
+			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
+		>;
+	};
+
 	pinctrl_uart3: uart3grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x140
