U-Boot 2019.10+zeus.TQMLS1028A.BSP.SW.0106-35-gf8db8d8 (Apr 29 2022 - 08:24:51 +0000) SoC: LS1012AE Rev2.0 (0x87040020) Clock Configuration: CPU0(A53):1000 MHz Bus: 250 MHz DDR: 1000 MT/s Reset Configuration Word (RCW): 00000000: 0800000a 00000000 00000000 00000000 00000010: 35080000 c000000c 40000000 00001000 00000020: 00000000 00000000 00000000 00004412 00000030: 00000000 00800120 00000096 00000000 Model: MBLS1012AL starterkit Board: KION IOBox DRAM: 446 MiB Using SERDES1 Protocol: 13576 (0x3508) WARNING: Calling __hwconfig without a buffer and before environment is ready MMC: FSL_SDHC: 0 Loading Environment from SPI Flash... SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB OK In: serial Out: serial Err: serial MAC from eeprom: 00:d0:93:30:fe:9a Warning: MAC addresses don't match: Address in EEPROM is 00:d0:93:30:fe:9a Address in environment is 00:d0:93:30:fe:88 TQMLS1012AL EEPROM: ID: TQMLS1012AL-AA.0200 SN: 75346308 MAC: 00:d0:93:30:fe:9a MBLS1012AL EEPROM: unknown hardware variant unknown serial number invalid MAC gpio_hog_probe_all Net: SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB PFE class pe firmware PFE tmu pe firmware Configured ETH_PHY_RST pin ETH_PHY_RST pin cleared ETH_PHY_RST pin set again PFE MDIO_SGMII_CR reg: 0x1140 PFE MDIO_SGMII_SR reg: 0x9 PFE MDIO_SGMII_DEV_ABIL_SGMII reg: 0x4001 PFE MDIO_SGMII_PARTNER_ABIL reg: 0x4020 KSZ9467S phy probed! Starting configuration of KSZ switch.... KSZ9567S REGISTER 0x1F0000 = 0x1140 KSZ9567S REGISTER 0x1F0001 = 0x1A9 # link is up KSZ9567S REGISTER 0x1F0002 = 0x7996 KSZ9567S REGISTER 0x1F0003 = 0xCED0 KSZ9567S REGISTER 0x1F0004 = 0x20 KSZ9567S REGISTER 0x1F0005 = 0x4000 # This bit indicates that the link partner has successfully received the page sent by this device. KSZ9567S REGISTER 0x1F0006 = 0x2 # This bit indicates that a page (auto-negotiation codeword) was received from the link partner. KSZ9567S REGISTER 0x1F8000 = 0x2400 KSZ9567S REGISTER 0x1F8001 = 0x19 KSZ9567S REGISTER 0x1F8002 = 0x1 # This bit is set when auto-negotiation is complete Switch started. SerDes reg 0x1EA0000: 0x426745E8 SerDes reg 0x1EA0004: 0x10800008 # Power down an unused PLL, PLL is off SerDes reg 0x1EA0008: 0x8004100 SerDes reg 0x1EA0018: 0x81000000 # Disables the reference clock amplifier and selects usage of the reference clock coming from the left, either from SoC or from another 10G Serdes PLL SerDes reg 0x1EA0020: 0x426745E8 SerDes reg 0x1EA0024: 0x108A0008 # Reference clock frequency select: 100 MHz ext or 125MHz internal SerDes reg 0x1EA0028: 0x8004100 SerDes reg 0x1EA0038: 0x80000000 SerDes reg 0x1EA0090: 0x48000000 SerDes reg 0x1EA0094: 0x0 SerDes reg 0x1EA00A0: 0x48008000 SerDes reg 0x1EA00A4: 0x80000001 # Enable CML analog buffer used to transition SoC reference clock to 10G Serdes SerDes reg 0x1EA00B0: 0x2804000 SerDes reg 0x1EA0200: 0x10000000 SerDes reg 0x1EA0208: 0x10000008 SerDes reg 0x1EA0220: 0x10000000 SerDes reg 0x1EA0800: 0xAA611080 SerDes reg 0x1EA0804: 0x1C4019 SerDes reg 0x1EA080C: 0x2800 SerDes reg 0x1EA0810: 0xF0FC01F SerDes reg 0x1EA0814: 0xF0F0EA8 # only reserved bits are different SerDes reg 0x1EA0818: 0x3006 SerDes reg 0x1EA081C: 0x5800 SerDes reg 0x1EA0820: 0x39000400 SerDes reg 0x1EA083C: 0x8000000 SerDes reg 0x1EA0840: 0x99650000 SerDes reg 0x1EA0844: 0x144C4099 SerDes reg 0x1EA084C: 0x98282A00 SerDes reg 0x1EA0850: 0x1F SerDes reg 0x1EA0854: 0xFA8 SerDes reg 0x1EA0858: 0x10283000 SerDes reg 0x1EA085C: 0x984DDA00 SerDes reg 0x1EA0860: 0x400 SerDes reg 0x1EA087C: 0x4000000 SerDes reg 0x1EA08C0: 0x31651100 SerDes reg 0x1EA08C4: 0x445002A SerDes reg 0x1EA08CC: 0xAA502887 SerDes reg 0x1EA08D0: 0x1F SerDes reg 0x1EA08D4: 0xFA8 SerDes reg 0x1EA08D8: 0x10223010 SerDes reg 0x1EA08DC: 0x502880 SerDes reg 0x1EA08E0: 0x500 SerDes reg 0x1EA08FC: 0x8000000 SerDes reg 0x1EA1000: 0x20000000 SerDes reg 0x1EA1804: 0x8BF SerDes reg 0x1EA180C: 0x0 SerDes reg 0x1EA1814: 0x3F SerDes reg 0x1EA181C: 0x0 PFE MDIO C22 reg 0x0: 0x1140 PFE MDIO C22 reg 0x1: 0x2D # This link is valid; AN Complete PFE MDIO C22 reg 0x2: 0x83 PFE MDIO C22 reg 0x3: 0xE400 PFE MDIO C22 reg 0x4: 0x4001 # Read only bit set to 1 when device has received three consecutive matching ability values from the link partner PFE MDIO C22 reg 0x5: 0x4020 # Read only bit set to 1. when the Link Partner Copper Interface advertises that it has that received three consecutive matching ability values from the device and different reserved bits PFE MDIO C22 reg 0x6: 0x6 # Set to 1 to indicate that a new page has been received with new partner ability available in the PCS register PARTNER_ABILITY. The bit is set to 0 (Reset value) when the system management agent performs a read access. and reserved bit PFE MDIO C22 reg 0x7: 0x0 PFE MDIO C22 reg 0x8: 0x0 PFE MDIO C22 reg 0xF: 0x0 PFE MDIO C22 reg 0x10: 0x0 PFE MDIO C22 reg 0x11: 0x1 PFE MDIO C22 reg 0x12: 0x400 PFE MDIO C22 reg 0x13: 0x0 PFE MDIO C22 reg 0x14: 0xA eth0: pfe_eth0 Hit any key to stop autoboot: 0 =>