I want to use the Port E as GPIO in 9S12DT256, but I can not config the PEAR. In the datasheet I found it, I don't know how to use Port E as GPIO. Thanks.
The port E are general purpose input or output pins link other standard S12 MCU.
PE7 - NECLK – setup in the register ECLKCTLPE6, PE5 – general purpose input or output pinthe same functionality as in S12 devices (MODB, MODA during reset)
PE4 - ECLKX2 – setup in the register ECLKCTLPE3, PE2 – are controlled by MCU mode setup. If the MCU is used in expanded mode then these bits are controlledby MEBI interface.PE1(\IRQ) – input only (if \irq is used then it must be enabled in IRQCR register)PE0(\XIRQ) – input only (\XIRQ functionality is used only if X bit in the CCR is cleared. However this pin is able to wake up the MCU from stop mod even \XIRQ is not used)
also you should set registers DDRE, RDRIV and PUCR to get required functionality.
By default in single chip mode all PORTE pins are GPIO.
Normal BDM debugger setup involves special single chip mode, where NECLK bit is clear and you have ECLK signal outputed to PE4. To disable ECLK on PE4 you should set NECLK.
Special care is required for PE5-7 pins. Since these are MODA, MODB and XCLKS inputs on reset, they should be not driven at power on/reset by hardware, you are interfacing. Pull down/up resistors should determine required initial MODA,MODB and XCLKS settings at power on or resets. You may use these pins as GPIO outputs, but then you should provide that no excessive capacitance or load is applied to these pins at power on / reset, which may make your MCU boot with wrong MODA / MODB / XCLKS settings.
Because of the reasons stated by Kef, I would advise against using PE5-7 as GPIO. I've been troubleshooting HCS12s for almost 10 years, and one of the most common design errors seem to be either obscure circuits connected to PE7 / XCLKS, or wrong logic level applied to it at startup.
Please note that Freescale have made some wonderfully confusing documentation over the crystal selection, where they state that XCLKS should be high to select a certain oscillator in the oscillator part of the manual, while at another place in the device user guide, they say that PE7 should be low. The secret trick here is to realize that the Freescale manual actually isn't contradicting itself, because XCLKS is referred to as /XCLKS in the real world outside the manual, it is an inverted signal.
Plenty of HCS12 designs have failed because of this - if you pick a Colpitts oscillator but have a Pierce outfitted on the PCB, the CPU will disapprove, but start up in self-clock mode ("limp home"). 5V on PE7 pin at startup = Colpitts, 0V on PE7 pin at startup = Pierce or external oscillator.
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