My objective is to get a fast stable BUSCLK (internal osc) from a QE8 as simple as possible. This is what I've read in AN3499 (Clock Options on the HC9S08 Family) about the ICS in section 2.1:
Table 4 shows that with DRS bits = 00 and DMX32=1 that I get a reference freq of 32.768K and a DCO output freq of 19.92M, which can give me a BUSCLK of 9.96M. It also states in section 220.127.116.11 (about the ICS Status & Control reg) that
"The register also contains the DCO maximum frequency bit (DMX32) that determines if a finely tuned reference frequency of 32.768 kHz is used. When using this reference, the DCO multipliers are greater when compared to general reference frequencies and this provides a fixed DCO output."
When I read "a finely tuned reference frequency..." it made me wonder WHO does this "finely tuned" thing, me via the trim bits, or Freescale in the chip? Table 4 makes me think it is independant of the trim bits.
Anyone have any experience using it this way?