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GCC compiler in CW10.1 optimized for M4?

Question asked by Richard Sloan on Oct 14, 2011
Latest reply on Dec 3, 2011 by MICHAEL SUTTON

Is it aware of optimizations for M4? It seems not to be......

 

would you not expect

 

static inline int MULSHIFT32(register int x, register int y)
{
  return (((Word64)x*(Word64)y)>>32);
}

 

SMULL  R3, R2, R1, R0
MOVS  R0, R2

 

to be compiled to a couple op-codes?

 

Richard.

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