I am using the I2C interface and have a strange clock frequency problem. My system oscillator is 24 Mhz with a predivide (CCHR=2) divide by 3, and a PLL multiply by 8 for a system clock frequency of 64 Mhz.
Setting the I2FDR register with 0x0d (divide by 160) results in a slightly slow clock frequency of 381 KHz. If I use the 0x30 (also divide by 160) I get the correct frequency of 400KHz. Trying other values from the 2nd or 4th column of the I2FDR work as expected, but selecting the same divider from columns 1 and 3 result in a slightly slow frequency.
I cannot find any information on what the individual bits of the I2FDR register do. Why are there multiple frequency dividers?
Any help would be appreciated.