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Proper BASEPRI on Kinetis when interrupt priorities are used

Question asked by Konrad Anton on Sep 2, 2011
Latest reply on Sep 2, 2011 by David E Seymour

Hello all,

 

In my K60-based MQX system, I need interrupts of different priorities. So far, I've used _bsp_int_init to assign priorities to the  interrupt vectors I want to have high priority, leaving ordinary interrupts untouched. When I look at the NVIC_IPRxx registers in the CodeWarrior 10 debugger, I see priority 0xC0 everywhere, except for my high-priority interrupts, some of which are at 0x80, some very urgent ones at 0x60. So far, so good.

 

On entering an ISR installed using _int_install_isr, I read BASEPRI as 0xC0, and PRIMASK as 0, i.e. every interrupt with priority 0x80 or 0x60 is welcome to interrupt this ISR. Hence, my 0x60 urgent ISR can be interrupted by a less-urgent 0x80 ISR, even if the first C instruction in its body is _int_disable().

 

Are my observations and conclusions correct? Is there a way I can achieve prioritized interrupts without using kernel ISRs everywhere?

 

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