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PLL on MPC56xx devices

Question asked by David Brown on Aug 29, 2011
Latest reply on Aug 30, 2011 by David Brown

I am trying to understand the FMPLL settings on an MPC5675K device (but the same applies to the MPC5643L and MPC5554 that I've tried).

 

The board I am using has a 40 MHz crystal.  I have got the default settings for the FMPLL, and have set the external clock pin to show the system frequency divided by 8.  I've measure it as 129.9 MHz - a value I have confirmed by checking the speed of the decrementer timer in the cpu.

 

But the FMPLL settings are IDF 1 (giving an input division of 2), ODF 1 (giving an output division of 4), and NDIV 0x40 (giving a pll loop division of 64).  Plugging these numbers into the formula for frequency in the reference manual gives me 320 MHz.

 

I can't remember the figures off-hand, but I had the same situation with the MPC5554 and MPC5643L that I also tested briefly.

 

If I change the IDF and ODF settings to half the expected frequency, the measured frequency is halved.  So I have no doubt that I'm using the PLL for my clocks.  But I would very much like to find out why the calculations give 320 MHz and the measurements give 129.9 MHz.

 

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