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A general question about MPC83xx Load/Store Unit.. Just for personal interest.

Question asked by xueyuan bai on Aug 27, 2011
Latest reply on Oct 9, 2011 by xueyuan bai

Hello, here is a question with Load/Store Unit. The CPU is MPC837xE

 

Let's say that,  there is one Nor Flash locating at CS0 of eLBC,

 

and its data width is 16-bit, that is, 16-bit data comes  out when it is read each time.

 

There is no hardware signal like ' byte selection from the 2 bytes ' .

 

The base address of CS0 is 0xFF800000.

 

now, let's read one byte in this nor flash, for example,

 

unsigned char ch = 0;

 

ch = *(unsigned char *)(0xFF800000);

 

After disassemble,   this C statement is as following in assembly language:

 

lis r5, 0xFF80

 

lbz  r31,  0(r5)   //  an register  indirect with immediate index mode addressing

 

this is the point  I am interested in .

 

lbz is a load instruction, which indicates a read command. and

0(r5)  indicates the address where  data locates.

 

This address will enter into Nor flash CS0 address space.

 

 READ command  and Address will validate CS0, OE#, address lines  in Nor Flash.

 

After this read, Nor Flash chip will return 2-byte data to eLBC.

 

But,  how is it determined that which of these 2 bytes data is needed ?

 

I am very curious about this ?

 

Is there another layer underneath the assembly language?

 

Assembly language codes will  be transformed into kinds of hardware signal, aren't they ?

 

Is there anyone who can help with this question and go any further?

 

 

 

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