TomE

MCF5329: LCDC Maximum Frequency Confusion, 20, 27 or 40MHz?

Discussion created by TomE on Aug 12, 2011
Latest reply on Nov 7, 2011 by TomE

What's the maximum pixel clock rate on the MCF5329 LCD Controller?

 

If you're doing a new design and are trying to work this out there's only a 30% chance you'll find the "right" answer.

 

According to:

 

    MCF5329RM.pdf

    MCF5329 Reference Manual

    22.3.7 LCDC Panel Configuration Register (LCD_PCR)

    Note: Set PCD so that the LCD_LSCLK frequency is less than one-third (TFT mode)

             or one-fourth (CSTN mode) of the system bus clock (fsys/3) frequency.

    "LESS THAN 1/3" is 1/4, so the maximum frequency is 80MHz/4 or 20MHz.

 

According to:

 

    AN3606.pdf

    Understanding LCD Memory and Bus Bandwidth Requirements

    Table 2. Bus Bandwidth Usage for Color LCD Panels

    Currently, the ColdFire processors that include the graphical LCDC

   support a maximum pixel clock frequency of 26.66 MHz;

 

According to:

 

    MCF5329DS.pdf

    5.10 LCD Controller Timing Specifications

    T1 LCD_LSCLK Period   min = 25ns,  max = 2000 ns

    Which is 40MHz.

 

I suspect that only the App Note is correct. The Reference Manual probably meant to state "less than or equal to 1/3" but doesn't. The control registers allow for a 40MHz clock (as per the Data Sheet), but it isn't a supported frequency.

 

It isn't documented anywhere that at 26.66MHz the pixel clock has a 30% duty cycle. That might cause problems with some video hardware or panels.

 

Tom (A Random Poster)

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