I had a similar question, so I thought I would post my analysis even though this post is getting old. Basically, it doesn't look like you can assume that. In order to get the 14.5 ENOB you need to use differential mode, and set the averaging to 32 samples. I did my calculations for single ended, which gives a max ENOB of about 13.5.
For a K60-100MHz part, I can set the ADC clock to a max of 6.25Mhz because the max is 12Mhz for 16bits, and there are only power of two clock dividers. This gives me a sample+ convert time of 140.42 usec, or about 7121 ksps. Differential is even slower.
If you get rid of the averaging you loose about a bit of ENOB and get a sample+convert time of about 6.5 usec, or about 154 ksps. Differential will be a little bit slower again, and you can't switch between as many channels.
You will most likely need to check the DS & RM for the specific part and check to see what you can clock the ADC at.
