gang chen

MCF54416 UBOOT Debugging

Discussion created by gang chen on Jul 5, 2011
Latest reply on Jul 7, 2011 by gang chen




    I have been debugging the problem for a while. So the description here will be a little bit long.

    download u-boot to spi flash and system can't boot.


    1. using CodeWarrior's "load memory" to load uboot's first 1K to internal ram. we can single step while pc is still pointing to the internal SRAM. one it jump to the DDR RAM. system died.

     2. using CodeWarriros's "load memory" to load the uboot's first 1k and before uboot's Jump to external ram (0x47e00400), using CodeWarrio's "loading memory " to load uboot to external ram, starting from 0x47e00000. still failed . so using CW's "saving memory", found the content of the DDR RAM is different to uboot.bin.  I tried to stored three times, but three results are different and none of them is correct. FAE from freescale told me that DDR RAM reading from BDM is not trustable, but I am suspicious about this.


    3. we got a working project from freescale and this working project is using DDR RAM to excute. So after this project is running, we stop the system, and download the uboot.bin by "load memory" to DDR RAM.  using "storing memory" again and found that the content of the DDR RAM is matching uboot.bin. and "change program counter" to 0x47e00400, at least we saw the following from the com port.

U-Boot 2009.08 (Jul 01 2011 - 14:49:16)

CPU:   Freescale MCF54416 (Mask:a1 Version:1)
       CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 62.500 MHz
       INP CLK 50 MHz VCO CLK 500 MHz
Board: Freescale M54418 Tower System
SPI:   ready
DRAM:  128 MB


so I would conclude that DDR RAM is causing the problem. and once DDR RAM is right configured, uboot will starts to work.(may have other bugs....) I have tried to compared the DDR_CRs between uboot and working project. And it showes that only DDR_CR41 is different. uboot.bin is using 0x00C80064, and working project is using 0x00000064. What this meaning? any register will also affects DDR setting?


Any suggestion to this ?




Br, Chen Gang