Myles Scott

ADLSTAT REGISTER / High Limit Interrupt Help Please!

Discussion created by Myles Scott on Jun 27, 2011
Latest reply on Jul 12, 2011 by Alexey

Hi I have a MC56F83XX board and upon reading the manual I come up with this paragraph.

&quote;2.12.7 ADC Limit Status Register (ADLSTAT)

The Limit Status register latches in the result of the comparison between the result of the sample

and the respective limit register, ADHLMT0-7 and ADLLMT0-7. For an example, if the result

for the channel programmed in SAMPLE0 is greater than the value programmed into the High

Limit register zero, then the HLS0 bit is set to one. An interrupt is generated if the HLMTIE bit is

set in ADCR1. A bit may only be cleared by writing 1 to that specific bit. These bits are sticky.

Once set, the bits require a specific modification to clear them. They are not cleared

automatically by subsequent conversions."

I am not sure I understand this correctly. If I am trying to see if a bit that has triggered the high limit interrupt would this be the correct code? Obviously this code is just an example and the if logic is not conclusive. I have tried to look up other peoples code but haven't found any, the only thing I have found is Init code and I have seen people setting the ADLSTAT to FFFF, which seems to be the opposite of what I am doing. Any input is greatly appreciated. Thanks!

register word LimitStatusTmp; //Word that holds value of data

int Values[8]; AD1_GetValue((int *) Values); LimitStatusTmp = getReg(ADCA_ADLSTAT);

int Curr_High_A

int bit; //flag variable to set high bit number if (LimitStatusTmp & 0x0100) { bit = 8; } Curr_High_A = Values[bit-8]; clrRegBits(ADCA_ADCR1,0x0080);

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