Mark Likness

MCF5485 EPORT Interrupts

Discussion created by Mark Likness on Jun 21, 2011
Latest reply on Jun 22, 2011 by TomE

I have two external interrupt sources tied to the 5485 EPORT module.  One source is tied to IRQ2 the other to IRQ3.  Using a logic analyzer I can see that when IRQ2 is asserted during assertion of IRQ3 the ISR for IRQ2 never gets control.  It is as if the 5485 thinks IRQ2 never happened in this case.

 

I have tried using both falling-edge and level triggering and both behave the same way.  I am not using CodeWarrior (am using gcc) so the problem is not related to the much-discussed status register mask issue there (but even if it was, shouldn't that simply delay recognition of IRQ2 rather than cause it to be completely ignored?).

 

Bottom line, I am trying to understand what can make the Coldfire forget about a lower priority IRQ that happens to be asserted while a higher priority IRQ is asserted.  I am perfectly fine with IRQ3 preempting IRQ2 (I expect that), but only if IRQ2 is eventually recognized and processed.

 

Thanks for any thoughts and assistance.

Outcomes