Suzanne Eckardt

Power-on problems with 54455 Fast Ethernet Controller 0 (FEC0)

Discussion created by Suzanne Eckardt on May 26, 2011
Latest reply on Jun 17, 2011 by John Weil

We've been successfully running an application on custom 54455-based boards for months, mainly using revision 1M22H parts.  Some recent boards, using revision 2M22H parts, have been exhibiting power-on initialization problems on FEC0 - while FEC1 is consistently fine.  Even after setting both FECs in internal loopback mode, thereby eliminating the external PHYs from the configuration, FEC0 still doesn't operate properly.  Various types of external resets, however, seem to resolve the problem on FEC0.


When FEC0 is not operating properly: there is a valid transmit buffer descriptor queued, TDAR0 is set, the FEC is enabled in ECR0, all interrupts are enabled - but no interrupts are generated and no interrupts are shown as pending in EIR0.  The same application code is used to manage FEC1, and it operates as expected.


Does anyone know of any problems specific to FEC0??