Very tricky these CPUs. All of the address and data lines are exactly the reverse of most other chips and manufacturers (including Freescale itself, the ColdFire parts don't have all their naming reversed).
The MSB for data and address lines is "0" and can have the "value" "2^7", "2^15" or "2^31" depending on the specific bus width. Likewise the LSB is 7 for bytes, 15 for words and 31 for longs. Except when it isn't (LAD0 is 2^25, a weird number indeed).
EXCEPT for the MA0-MA13 lines which are different in being the only "normally" named pins on the part, and have to be connected one-to-one to the same pins on the DDR.
The Reference Manual should have more warnings, as everyone seems to get this wrong the first time they design with the PPC. There isn't that much to help people work out which bits are which and which bus-lanes are which. The "big clue" is that the DDR signals are called "MDQ[0:15]" and "MA[13:0]". Note the opposite numerical order. You just have to notice subtle clues like this.
UNLESS you're reading AN4107, the "Design Checklist" where that bus is called "MEMC_MA[0:13]" ,so there you have to know the author forgot to reverse the designation. You should be reading these checklists, they really look like they'd save you some problems.
I'd guess the only safe way to design a board is to reverse-engineer the pin functions from the Evaluation Boards.
Here's a puzzle that is pretty tough to work out
Table 11-2. Enhanced Local Bus Controller Detailed Signal DescriptionsLA[16:25] O Nonmultiplexed address bus. All bits driven on LA[16:25] are defined for 8-bit port sizes. For 16-bit port sizes LA[25] is a don’t care.LAD[0:15] I/O Multiplexed address/data bus. For a port size of 16 bits, LAD[0:7] connect to the most-significant byte lane (at address offset 0), while LAD[8:15] connect to the least-significant byte lane (at address offset 1). For a port size of 8 bits, only LAD[0:7] are connected to the external RAM.
So how are the addresses delivered across those pins? With other chips I'd expect the non-multiplexed address pins to deliver the lower addresses while the multiplexed ones deliver the upper ones (and then the data), usually in blocks of 8 bits.
So are the addresses:
LA16 ... LA25 ... LAD0 ... LAD15 with the data bus at the bottom, or:
LAD0 ... LAD15 ... LA16 ... LA25?
The "for 16-bit port sizes LA[25] is a don't care" implies it is the LSB address, which means the addresses are LAD[0:25]. That sort-of makes sense, except that means LAD[0] doesn't carry the address bit "2^31" or "2^23", but carries "2^25". So on any other chip it would be "A25". Unexpectedly, the data bits seem to be delivered on the upper 16 bits of a 26-bit bus!
All this bit-ordering comes from the original IBM core documentation.
Tom
