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QD4 internal clock/FLL unstable? Large production facility issue, LED light flickering ...

Question asked by Emil Kovatchev on Apr 1, 2011
Latest reply on Apr 7, 2011 by David Payne



we are using a small QD4 to control a LED daytime running light appication, which is in pre-production status. Suddenly, customer complains about visible LED light flickering.


The LEDs are dimmed by 200Hz PWM signal. Once on every 100 pieces, right after the first flash , one QD4 does exhibit very unstable dimming PWM, both frequency and duty are jittering by some 20%, which - unfortunately - results in visible and unacceptable LED flicker...


Moreover, the jitter is temperature dependent, almost disappearing when the uC is getting warmer, but returning back when uC is getting colder again.


This is a hardware PWM with a dedicated timer, driven by the internal clock.


I am suspecting the FLL loop in not being able to lock in, but why, on earth, would this happen only once at 100 and not with every single piece...?


How can I tell with the QD4 if the FLL has really engaged and locked in? I can't find any hint in the datasheet, I don't see any flag, signalling a proper FLL operation.


Any help or hints would be highly appreciated!


Here is the ICS initialization routine, straight out of the CodeWarrior InitializationExpert, we did't change anything there, in fact, those are simply the default register settings after POR:


  //Initialize ICSTRM register from a non volatile memory
  ICSTRM = *(unsigned char*far)0xFFAFu;
  //Initialize ICSSC register from a non volatile memory
  ICSSC = *(unsigned char*far)0xFFAEu;  
  //internal clock selected
  ICSC1 = 0x06u;                        
  //ICSOUT is TWICE the bus frequency!!!
  //the bus frequency is 4000000Hz (8Mhz divided by 2, BDIV = 01, default after reset!)
  //ICSC2: BDIV=1,LP=0
  //BDV = 1 defines the ICSOUT frequency as clock freq (16Mhz) divided by 2!
  //since ICSOUT is twice the bus frequency, the BUS frequency is 4 MHz !!!
  ICSC2 = 0b01000000u;