David Krauss

writing to internal Flash and interrupt latency

Discussion created by David Krauss on Feb 10, 2011
Latest reply on Feb 17, 2011 by bigmac

While writing to or erasing the Flash memory on an HCS08 or ColdFire v1 Flexis MCU, read accesses are illegal and return invalid data. Assuming all ISRs are in Flash, no interrupts may be serviced while Flash is writing or erasing. This takes up to 20 ms, which is a bit long.

Is there a way to abort a Flash command in progress (FSTAT_FCCF = 0) such that read access is restored? It appears the user manuals for the MC9S08MP16 and the MCF51JM128 differ slightly in wording:

MC9S08MP16RM §4.5.5: Any of the following actions will cause the access error flag (FACCERR) in FSTAT to be set. FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.

MCF51JM128RM §4.5.3.1: The FACCERR flag is set during the command write sequence if any of the following illegal steps are performed, causing the command write sequence to immediately abort:

According to the manuals, the ColdFire Flexis part immediately aborts a write if I write to any Flash register while a command is in progress, but the HCS08 part does not. The only condition where the HCS08 manual specifies FACCERR while FSTAT_FCCF = 0 is (perhaps) issuing a STOP instruction, which is inconvenient to work into a program. Is this really supported on either part, or both, and are there any other caveats (such as waiting for a few cycles to ensure the command has been aborted)?

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