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DSP56321: HELP - DMA5 transfer interrupt not serviced

Question asked by Thomas Lorenz on Feb 7, 2011
Latest reply on Feb 8, 2011 by Thomas Lorenz

After adding a modification to our existing code I have the effect, that sporadically the dma5 interrupt is not serviced (althougt the DMA transfer itself is executed).

The DMA transfer is triggerd in a subroutine during a priority 2 irqa service routine.

We use the DMA5 to perform a "dummy" transfer in order to invoke an ipl 1 interrupt.

Anyway I checked that the DMA-tranfer is executed and it is.

Sequence during irqa that causes the error:

In c:

start500(2);

//new code start

if (INT_EN.B.VM_IEN)   

irqa_max_time=3600;

//new code end

void start500(int){

...

DCR5.B.DE=1;

}

In asm:

jsr Fstart500

jclr #23,y:<<$FFFFC4,L265

move #$E10,r6

move r6,x:smileysad:r7)

L265:

Fstart500:

...

bset #23,x:<<$FFFFD8

(stall 1 cycle)

rts

What makes the error disappear is replacing DCR5.B.DE=1;

at the end of start500() or changing the code order.

In c:

void start500(int){

...

//Interrupt to invoke 500µs Task

    if (yitst_inttest[9]) //no error

        {DCR5.I=(int)0xDa0241;__asm(" nop");}

    else //error

        {__asm(" nop");DCR5.B.DE=1;}      // generate DMA    

}

In asm:

L171:

move y:Fyitst_inttest+9,b

tst b

beq L172

(stall 1 cycle)

movep #$DA0241,x:<<$FFFFD8

nop

rts

L172:

nop

bset #23,x:<<$FFFFD8

(stall 1 cycle)

rts

Register Setup:

    DSR5=(int _X *)&yisys_debug;

    DDR5=(int _X *)&xisys_debug2;     // dummy write

    DCO5=0;                     // 1 tfr

    DCR5.I=0x5a0241;        // Interuppt enabled,Transfermode DE, Priority 1 ,no continous mode, Request_source IrqA,no destination update, no source update, no 3d adressing, Countermode C, destination x-mem,source y-mem

    IPRP.B.T0L=3;                    // Timer Int: Priority=3

    IPRC.I=(int)0x400e3e;            // INT A: neg edge, Prio=2 Bits 2..0=110

    // INT B: neg edge, Prio=3 Bits 5..3=111

    // INT D: neg edge, Prio=3 Bits 11..9=111

_asm(" ori #$01,EOM");        //OMR.B.CDP0=1; 01

_asm(" andi #$1d,EOM");        //OMR.B.CDP1=0;

What could prevent the dma5 isr from being serviced!?

 

Channels in error.jpg:

 

ch1: error trigger

ch2: xisys_debug2 (DMA transfer target, source has value 12, set to -1 at irq_a start)

ch3: yisys_check500us (set in start500(), reset in dma5_int() isr)

ch4: yitst_inttest[0] (counted up in dma5_int())

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