I am implementing a single channel Analog-to-Digital read, using MC9S08LC60, but I am having inconsistent results.
Here is my setup:
* In most use the module is connected to a 12V battery, and it also uses 3V backup batteries
* A regulator drops the 12V to 3.3V
* A diode is between the 3.3V and the backup batteries, with the feed going to the MCU's Vdd
* The Vdd while on the backups is 2.8-2.9V
* PTA0 has a line going to a point between the regulator and the diode, hence the read will be approx. 3.3V when the 12V is connected
* The current draw is 3.7mA in run
* PTA0 is initialized before the main loop:
MOV#%00010000,ADCCFG ; ADC
MOV#%00000001,APCTL1 ; Enable PTA0 as a ADC pin
* Then in a quarter second loop:
CLRADCSC1; COCO, AIEN, ADCO, ADCH (4:0)
BHIxxxx ; >250 = voltage from VR, 3.2V, lower V if only from internal batts
Sometimes it does not load ADCRL into A, hence a false branch occurs. Moreover, I could use this read very early in Vreset but it is even more inconsistent there.
Note that every ADC read follows a port initialization and that with a PE BDM the correct values are shown in ADCRL, $FF when the 12V source is connected and approx. one half that value when on backup batteries (2.8-2.9VDC). But it doesn't consistently load ADCRL and the failure results in $00 in A with the debugger showing $FF in ADCRL, if on 12V.
What can be done to make each read reliable?