Can anyone explain to me why PTE1 is an input-only pin on the S08DZ? This makes no sense at all to me. It is shared with SCI Rx functionaity, but so is PTF, and all PTF pins can be used as I/O.
This is so typical for Freescale. They make a CPU with 6 ports that are -exactly- identical, except for a tiny footnote to the DDR register for PTE1 stating that it is input only. I cannot begin to express how incredibly moronic this is! No other MCU manufacturer on the market does insane, illogical things like this, but at Freescale it is tradition!
I remember the same thing on the HCS12Dx256 where you could map the SPI2 to different ports, but if you did, the clock and SS pins were merrily switched.
Unless you read the whole manual in detail while at the same time possessing photographic memory, you cannot possibly catch thing like this at design stage. As a sane engineer, you assume that sane people have routed the bond-outs. You think "ok if ports A to F work exactly the same, nobody in their right mind would change the functionality of a single pin on one of them".
This moronically designed little pin on the S08 now forces my company to redesign all PCBs. Just as we had to do for the moronically designed SPI2 routing on the S12 some years ago. No doubt hundreds of other companies has fallen into the same traps.
It is pretty obvious that some real nerd is in charge of the pin routing of Freescale MCUs, without a clue of the real world works outside of his little QFP.