In the SPI functional description, it mentions that when CPHA = 0 in the SPIxC1 register, that only a single transfer can take place when the SPI is in slave mode for each time /SSx goes low (refer section 14.5.1).
But, what is not explained, and what we grappled with for several hours, is the fact that you CANNOT load new data into SPIxD when /SSx is low if you are in slave mode and CPHA = 0. At least, this is what we determined for SPI port 1.
If we loaded SPI1D on power-up with data (say, 0xAA), then the first time the master transfered a byte to us, we'd shift the 0xAA byte back to it. So far, seemingly so good.
But, if when we got the interrupt for SPI receiver full (SPI1S bit SPRF set), and in the ISR we tried to put another data byte (say, 0x55) into the SPI1D (to transmit it), it would NEVER appear on the SPI bus back to the master, even after /SS1 had gone inactive and then active again for the next transfer. We would NEVER see the 0x55 byte. It was as if it was being thrown out of SPI1D, although looking at the object code and single-stepping in the debugger showed it was being put there.
Any ideas ?
At the very least, I'd hope Freescale could document this behavior a bit more clearly in the Reference Manual !