The manual, MCF54455RM, states that, during the serial boot load, the SRAM base address is set to 0. The SRAM section says that the base address has to be in the range 0x80000000 to 0x8FFF8000.
What's going on?
Section "12.4.3 Execution Transfer" of the Reference Manual is going on.
4. The actual memory that responds to the reset vector fetch depends on whether serial boot load is requested: — If SBFSR[BLL] is cleared, the reset vector fetch is handled by the FlexBus module, and whatever external memory is mapped at address 0, governed by the user-provided setting of RCON/CCR[FBCONFIG]. — If SBFSR[BLL] is set, the reset vector and boot code are read from the on-chip SRAM. (The SBF enables the SRAM and maps it to address 0 via the RAMBAR before control of the processor is restored to the ColdFire core.) The reset vector (initial stack pointer and program counter) should point to locations in the on-chip SRAM,
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