MCF5329 LCD Controller "Self Refresh" mode, how to recover/ exit this mode?

Discussion created by TomE on Sep 27, 2010
Latest reply on Nov 7, 2010 by TomE

I'm looking for a simple way to disable the video output from the MCF5329 LCD controller.


I thought I'd found it in the "LCD Controller Self Refresh Mode". I can enter this mode, but I can't get the chip out of this mode. Does anyone know how to exit this mode?


The "LCDC Refresh Mode Control Register (LCD_RMCR)" has a "SELF_REF" bit documented as:



Self-refresh mode enable.0 Disable self-refresh.1 Enable self-refresh.1. On entering self-refresh mode, the LCD_LSCLK and LCD_D[17:0] signals stay low. HYSN and VSYN operate normally.2. Except for the SSA, BGLUT, and GWLUT registers, all configurations must be performed before enabling the LCDC to avoid a malfunction.3. The SSA must always match the address range of the RAM selected. If the user wants to switch between various types of RAM, the LCDC must be disabled before switching.

 If I set the SELF_REF bit the video RG and B outputs to to Black and the Sync signals keep running, just as advertised. That seems to do what I need.


I need to reenable the video later. If I then clear the SELF_REF bit, the controller seems to lock up. No video and no sync. I have to reset the whole CPU to get it back to working again.


Surprisingly, the "Self Refresh" mode (whatever it is) will generate the sync pulses even if I disable the LCDC Internal Clock bit in the Miscellaneous Control Register MISCCR[LCDCHEN]. Enabling or disabling this clock around changing the SELF_REF bit doesn't seem to make any difference.



Someone has asked about using this mode in an attempt to claw back some bus bandwidth, but there was no answer: