908JL3 manual discrepancies re timer overflow bit

[JimDandy]

In the 908JL3 manual rev 1.1 page 127 it tells us that the TOF bit "is set when the TIM counter resets to $0000 after reaching the modulo value programmed in the TIM counter modulo registers". Page 130 contradicts this by saying "When the the TIM counter reaches the modulo value, the TOF becomes set".

One says TOF set =at= modulo value rollover, the other says set at last count =before= modulo value rollover.

Rev 4 of the same manual consistently says TOF is set at last count before modulo value rollover.

If it is on the last count it has not in fact overflowed, so why is the OVERFLOW bit set then? Should it not in fact be set when the numbers click over to zero???

[JimDandy]

Further to this, with the old '705P9 timer, it's manual says "TOF is automatically set when the timer counter register changes from $FFFF to $0000". This is then 1 count AFTER the '908 timer.

[bigmac]

Hello,

The Reference manual TIM08RM contains more detailed timing information.  The waveforms of fig. 41 and fig. 42 show that the overflow flag is set following the negative clock transition, the same transition that causes the count to change from the modulo value to zero.

Regards,

Mac

[JimDandy]

The waveforms of fig 41 make perfect sense. Exactly the way I imagine things.

But... page 54 of that same manual says:

"When the timer counter reaches the modulo value, the TOF flag is automatically set by hardware, and the timer counter resumes counting from $0000 at the next clock."

That appears to say the TOF is set 1 count before overflow...

Although, if we set the modulo to say 50 then it counts up to 49 and then rolls over to 0 for a 50 count cycle. If we say zero is the final (i.e. modulo) count then the statement in the manual makes sense - I think.

[bigmac]

Hello,

For a 50 cycle count the TMOD value requires to be set to 49.

One possible method of proving the flag setting point might be to:-

1. Set the prescale value to a reasonably high value so that the overflow interrupt latency period will always be significantly less than a TIM clock period, and to enable overflow interrupts.  For this test I suggest that the TMOD value remain at the the default.
2. On entry to the ISR code, immediately read the current TIM counter, and maybe send the result to a software SCI send, or maybe light one of a number of LEDs, dependant on the value..

The interrupt will not occur until the flag becomes set.  This test should use actual hardware, rather than emulation.  If fig. 41 is correct, the count value should be zero.

Regards,

Mac