CFV2 gpio input pull-up on reset question?

[RichTestardi]

Hi,

Someone asked me a question I don't have a good answer for, so I'm hoping someone else might have one...

Basically, on reset, CFV2 configures gpio pins for digital input.  Additionally, on reset, CFV2 (unlike CFV1) also automatically enables internal pull-ups on these pins.

This means that during the time (glitch) between reset and when the CPU can reconfigure these pins for (strong) digital output, the MCU is driving (albeit, weakly) a logic "1" onto lines that might be sensed by the external circuitry.

Why is this OK?  (Vs. the CFV1 behavior of needing the CPU to explicitly enable the pull-ups.)

It seems this requires a lower-value external pull-down to avoid the issue, if the external circuitry is susceptible to the glitch -- and the internal pull-up and the external pull-down duel during the glitch period, and then the external pull-down draws current forevermore when we later have to drive the pin high.

Is this just a "six of one, half dozen of the other" issue, in that half the circuits will be susceptible no matter what you choose?  Or are the "dueling pull-up/pull-downs" a reason for having the pull-ups need explicit initialization, allowing the use of a higher-value external pull-down?

Thanks for any input.

-- Rich

[TomE]

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Rich T wrote:

Basically, on reset, CFV2 configures gpio pins for digital input.  Additionally, on reset, CFV2 (unlike CFV1) also automatically enables internal pull-ups on these pins.

...

Why is this OK?  (Vs. the CFV1 behavior of needing the CPU to explicitly enable the pull-ups.)

 

-- Rich

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They don't make this obvious in the manuals do they!

I'm reading the MCF5235 Reference Manual. The only mention apart from listing pull resistors on the JTAG pins is a fine-print note under the pin tables saying "Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM.".

I had to read the "Electrical Characteristics" document to find the specs of the "Weak Internal Pull Up Device Current", which is 10-130uA, and has a note stating "Refer to the MCF5235 signals section for pins having weak internal pull-up devices.". But the Reference Manual says "pullup" and not "weak internal pull-up" so it is a stretch to think that these are the same things, but they probably are.

I think this would be a good feature if you could turn it OFF by using some "pull configuration egisters", but there aren't any. From what you said the CF1 had these control registers.

I suspect there's a tradeoff between flexibility and integration.

The most flexible approach requires the designer to add external pullups or pulldowns to ALL unconnected pins, and all pins that need to be "inactive" (pulled to a known level) during and after Reset. That may require 50 or more discrete resistors. Or you can ask the programmers to program all unused pins as outputs, but you still need to handle the "reset state". CPUs with 32-bit external busses are a problem. You don't want these floating diring low power modes as floating inputs can draw excess curreint in the input structures of the CPU and all chips on those busses.

The most integrated approach is to have these weak pullups, then unused pins can be left disconnected (and will be pulled safely), and any hardware requiring "known reset state" can be designed so that "high" is "inactive".

If you have "low is inactive" hardware, then add a cmos inverter to that pin. They're nearly as tiny and cheap as resistors now.

CF1 didn't default the pullups this but had controllable pulls. CF2 has pulls you can't control and CF3 doesn't have either. It seems the pendulum has swung back again. Maybe the resistors (or small FETx) occupy too much valuable silicon? Maybe the CF1 parts are mainly "microcontrollers" (internal RAM & FLASH)and the CF3 parts are mainly microcomputers (external RAM & FLASH) and the CF2 was in between?

> if the external circuitry is susceptible to the glitch

then it will certainly get glitched if the pin is left floating! Floating pins have "indeterminate" levels, which means you have no idea what they do. And the do different things from "cold power on" and from a quick off-on and a brownout. Their initial levels probably depend on what other tracks they're close to, and whether they're routed over a ground plane or a power plane, as the capacitance to that plane will probably couple voltage to the track on power on.