Someone asked me a question I don't have a good answer for, so I'm hoping someone else might have one...
Basically, on reset, CFV2 configures gpio pins for digital input. Additionally, on reset, CFV2 (unlike CFV1) also automatically enables internal pull-ups on these pins.
This means that during the time (glitch) between reset and when the CPU can reconfigure these pins for (strong) digital output, the MCU is driving (albeit, weakly) a logic "1" onto lines that might be sensed by the external circuitry.
Why is this OK? (Vs. the CFV1 behavior of needing the CPU to explicitly enable the pull-ups.)
It seems this requires a lower-value external pull-down to avoid the issue, if the external circuitry is susceptible to the glitch -- and the internal pull-up and the external pull-down duel during the glitch period, and then the external pull-down draws current forevermore when we later have to drive the pin high.
Is this just a "six of one, half dozen of the other" issue, in that half the circuits will be susceptible no matter what you choose? Or are the "dueling pull-up/pull-downs" a reason for having the pull-ups need explicit initialization, allowing the use of a higher-value external pull-down?
Thanks for any input.